LTC4260
29
4260fc
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However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
REV
DATE
DESCRIPTION
PAGE NUMBER
B
1/12
Revised Conditions and Min value for I
GATE(FST)
Corrected typographical error in Layout Considerations section
3
17
C
5/13
Removed erroneous temperature dot from ΔV
GPIO(TH)
Corrected Full Scale Voltage of SOURCE to 102V
Corrected I
LOAD
to I
GPIO
in G13
Illustrated a 16.5V clamp between GATE and SOURCE pins
Data Converter Section: Added a sentence describing noise averaging benefit of Δ
Σ
architecture
Added SMBT70A clamp to V
IN
line in Figure 13
Changed SMAT70B to SMBT70A in the Typical Application
3
4
7
10
15
25
30
(Revision history begins at Rev B)
