LT3480
17
3480fb
APPLICATIONS INFORMATION
Finally, keep the FB and V
C
nodes small so that the ground
traces will shield them from the SW and BOOST nodes.
The Exposed Pad on the bottom of the package must be
soldered to ground so that the pad acts as a heat sink. To
keep thermal resistance low, extend the ground plane as
much as possible, and add thermal vias under and near
the LT3480 to additional ground planes within the circuit
board and on the bottom side.
Hot Plugging Safely
The small size, robustness and low impedance of ceramic
capacitors make them an attractive option for the input
bypass capacitor of LT3480 circuits. However, these capaci-
tors can cause problems if the LT3480 is plugged into a
live supply (see Linear Technology Application Note 88 for
a complete discussion). The low loss ceramic capacitor,
combined with stray inductance in series with the power
VIAS TO LOCAL GROUND PLANE
VIAS TO V
OUT
VIAS TO RUN/SS
VIAS TO PG
VIAS TO V
IN
OUTLINE OF LOCAL
GROUND PLANE
3480 F09
L1
C2
R
RT
R
PG
R
C
R2
R1
C
C
V
OUT
D1
C1
GND
VIAS TO SYNC
Figure 9. A Good PCB Layout Ensures Proper, Low EMI Operation
Figure 10. A Well Chosen Input Network Prevents Input Voltage Overshoot and
Ensures Reliable Operation when the LT3480 is Connected to a Live Supply
+
LT3480
4.7μF
V
IN
20V/DIV
I
IN
10A/DIV
20μs/DIV
V
IN
CLOSING SWITCH
SIMULATES HOT PLUG
I
IN
(10a)
(10b)
LOW
IMPEDANCE
ENERGIZED
24V SUPPLY
STRAY
INDUCTANCE
DUE TO 6 FEET
(2 METERS) OF
TWISTED PAIR
+
LT3480
4.7μF
0.1μF
0.7Ω
V
IN
20V/DIV
I
IN
10A/DIV
20μs/DIV
DANGER
RINGING V
IN
MAY EXCEED
ABSOLUTE MAXIMUM RATING
(10c)
+
LT3480
4.7μF
22μF
35V
AI.EI.
3480 F10
V
IN
20V/DIV
I
IN
10A/DIV
20μs/DIV
+
