E
TERNA
LTP5901
AND
LTP5902
I
NTEGRATION
G
UIDE
7
Place R27, C5, and R29, C7,
close to U4 and U5,
respectively
eb_data_7
VSUPPLY
eb_data_0
eb_data_4
eb_data_6
eb_data_7
eb_io_cs0n
eb_io_cs0n
eb_io_le1
eb_addr_0
eb_io_le2
eb_io_le1
C2
0.1uF
0402
eb_addr_1
eb_addr_0
eb_data_3
eb_data_2
eb_data_5
eb_data_0
eb_addr_1
eb_data_1
eb_io_le2
eb_data_4
eb_data_3
eb_data_2
eb_data_1
eb_data_6
eb_data_5
Note:
Cypress STSOP-32 pin 1
is at pin 9, or A17
C3
0.1uF
0402
eb_addr_9
eb_addr_11
eb_addr_10
eb_io_le0
eb_io_cs0n
eb_io_le0
eb_io_oen
eb_addr_13
eb_io_le1_p
U4
74AUP1G58
SOT886
3
2
1
4
5
6
eb_io_le1
U3
74AHC573
DHVQFN20
OEn
1
D0
2
D1
3
D2
4
D3
5
D4
6
D5
7
D6
8
D7
9
GND
10
LE
11
Q7
12
Q6
13
Q5
14
Q4
15
Q3
16
Q2
17
Q1
18
Q0
19
VCC
20
GND
21
U1
74AHC573
DHVQFN20
OEn
1
D0
2
D1
3
D2
4
D3
5
D4
6
D5
7
D6
8
D7
9
GND
10
LE
11
Q7
12
Q6
13
Q5
14
Q4
15
Q3
16
Q2
17
Q1
18
Q0
19
VCC
20
GND
21
VSUPPLY_M
eb_addr_17
eb_addr_11
eb_addr_10
eb_addr_12
eb_addr_13
eb_io_le1_p
eb_addr_14
eb_addr_15
eb_addr_16
VSUPPLY_M
eb_data_6
eb_data_7
eb_io_le2_p
eb_addr_3
eb_data_4
eb_addr_2
eb_data_5
eb_addr_5
eb_data_2
eb_addr_4
eb_data_3
eb_addr_6
eb_addr_7
eb_data_1
eb_addr_9
eb_addr_8
eb_addr_7
eb_data_0
eb_data_1
eb_data_0
VSUPPLY_M
eb_data_6
eb_data_5
eb_data_4
eb_data_3
eb_data_2
R12
0
0201
eb_data_7
eb_io_le2_p
U5
74AUP1G58
SOT886
3
2
1
4
5
6
VSUPPLY_M
eb_io_wen
eb_data_5
eb_data_4
eb_addr_6
eb_data_3
eb_data_7
eb_data_6
Pulse Generator Circuits
eb_addr_5
eb_addr_4
eb_io_le2
VSUPPLY_M
R13
0
0201
eb_data_1
eb_data_0
eb_addr_16
eb_addr_14
eb_addr_12
R15
0
0201
eb_data_2
eb_addr_15
U2
CY62138FV30LL-45ZAXI
STSOP32
A0
20
A1
19
A2
18
A3
17
A4
16
CEn
30
IO0
21
IO1
22
VCC
8
IO2
23
IO3
25
WEn
5
A5
15
A6
14
A7
13
A8
3
A9
2
A10
31
A11
1
A12
12
A13
4
A14
11
IO4
26
IO5
27
VSS
24
IO6
28
IO7
29
OEn
32
A15
7
A16
10
A17
9
A18
6
eb_addr_17
eb_addr_1
eb_addr_0
eb_addr_8
eb_addr_3
eb_addr_2
C4
0.1uF
0402
C6
0.1uF
0402
eb_io_oen
eb_io_wen
eb_io_oen
eb_io_wen
R16
499
0201
R14
499
0201
25 mil traces for VSUPPLY_M
VSUPPLY_M
NoStuff R25 for 128KB
Place R26 and R28 close to U4 and U5,
respectively
R11
100k
0201
C5
30PF
0201
C1
0.1uF
0402
VSUPPLY_M
C7
30PF
0201
Figure 3
Table 2
Eterna Extended Memory Example Schematic (page 2 of 2)
Eterna’s External memory function has been tested with the BOM options shown in Table 2.
The RAM components shown have been selected for low power operation and their use will
result in an increase of a few μA of current consumption. For designs that are not energy
constrained, substitution of general purpose RAMs with equal or faster speed grades should
be possible. Substitution of the multi-function logic and octal latch components should be
done carefully to maintain the timing generated by the pulse generation circuits.
External Memory Reference Bill of Materials
Reference
Value
Vendor
Vendor P/N
R12, R13,
R15
0 Panasonic
ERJ-1GE0R00C