9
DEMO MANUAL DC252
DESIGN-READY SWITCHER
voltage rises above 0.1V to 0.8V. The turn-on may be
delayed as well. A switching regulator with soft-start may
appear to start up, then shut down and, eventually, reach
the correct output voltage. What happens is as follows: at
switching regulator turn-on, the output voltage is below
the active load’s turn-on requirements. The switching
regulator’s output rises to the correct output voltage level
due to the inherent delay in the active load. The active load
turns on after its internal delay and then pulls down the
switching regulator’s output because the switcher is in its
soft-start interval. The switching regulator’s output may
come up at some later time when the soft-start interval has
passed.
A switching regulator with foldback current limit will also
have difficulty with the unrealistic I-V characteristic of the
active load. Foldback current limiting will reduce the
output current available as the output voltage drops below
a threshold level (this level is 70% of nominal V
OUT
for the
LTC1736). This reduction in available output current will
result in the active load immediately pulling down the
output because the active load’s current demand remains
constant as the output voltage decreases. Most actual
loads do not behave like the active load I-V characteristics.
Actual loads normally have a V
IN
• C • f dependency, where
C is internal chip capacitance and f is the frequency of
operation. To alleviate the active-load problem during
testing, the active load should be initially programmed to
a much lower current value until the switching regulator’s
soft-start interval has passed and then increased to the
higher level. The switching regulator will supply the in-
creased current required according to the transient re-
sponse of the switching regulator. Output capacitance
needs to be sufficient to accommodate the current step
during the transient period, keeping the output voltage at
or above the foldback threshold of 70%.
Checking Transient Response
OPTI-LOOP compensation effectively removes the con-
straints placed on C
OUT
by other controllers (such as
restrictions on very low ESRs). The output capacitors
used in this demo board have very low ESRs; other types
may be substituted but be carefull to measure the load step
transient response and verify the specfications on output
voltage continue to be met during transients.
A partial list of low ESR capacitors that are suitable for this
application is included in the parts list. Each has its own
cost, size, ESL and other performance trade offs. Combi-
nations of capacitors have been shown to work well, too,
so feel free to experiment. An example of a combination
that works well is an OS-CON, 820
µ
F/4V capacitor in
parallel with a 180
µ
F/4V Matsushita SP series capacitor.
The SP capacitor tames the ESL-induced characteristic of
OPERATIO
U
Figure 3a. Dynamic VID Change, Burst Mode Operation Defeated
Figure 3b. Dynamic VID Change, Burst Mode Operation Enabled
252 F03a
PGOOD
5V/DIV
V
OUT
100mV/
DIV
I
L
5A/DIV
252 F03b
PGOOD
5V/DIV
V
OUT
100mV/
DIV
I
L
5A/DIV
