2
dc1791afa
DEMO MANUAL DC1791A
operAting principles
SPI signaling is controlled by the logic inputs
CS
, SDI,
and SCK.
SDOE
controls the SDO output and is normally
connected to
CS
. The corresponding isolated side output
signals are
CS2
, SDI2, and SCK2. SDO2 is the isolated
side SPI data input. All of the SPI communication channels
may be used as generic digital I/O.
I
2
C signaling is controlled by the logic inputs SDA and
SCL, corresponding to SDA2 and SCL2 on the isolated
side. The SCL channel is unidirectional supporting master
mode only I
2
C communication. SCL2 output is standard
CMOS push-pull drive. SDA signaling is bidirectional,
and includes an internal current source pull-up on SDA2
supporting up to 200pF of load capacitance.
Demo circuit 1791A is available in four configurations
supporting all versions of the LTM2887. Table 1 details
the demo circuit configurations.
Table 1.
DEMO CIRCUIT
INPUT VOLTAGE
COMMUNICATION
DC1791A-A
3.0V to 3.6V
SPI/Digital
DC1791A-B
4.5V to 5.5V
SPI/Digital
DC1791A-C
3.0V to 3.6V
I
2
C
DC1791A-D
4.5V to 5.5V
I
2
C
The demo circuit has been designed and optimized for low
RF emissions. To this end some features of the LTM2887
are not available for evaluation on the demo circuit. The
logic supply voltage V
L
is tied to V
CC
on the demo circuit,
and the ON pin is not available on the input pin header,
but may be controlled by jumper JP1. EMI mitigation
techniques used include the following.
1. Four layer PCB, allowing for isolated side to logic side
“bridge” capacitor. The bridge capacitor is formed be-
tween an inner layer of floating copper which overlaps
the logic side and isolated side ground planes. This
structure creates two series capacitors, each with
approximately .008” of insulation, supporting the full
dielectric withstand rating of 2500V
RMS
. The bridge
capacitor provides a low impedance return path for
injected currents due to parasitic capacitances of the
LTM2887’s signal and power isolating elements.
2. Discrete bridge capacitors (C3, C4) mounted between
GND2 and GND. The discrete capacitors provide ad-
ditional attenuation at frequencies below 400MHz.
Capacitors are safety rated type Y2, manufactured by
Murata, part # GA342QR7GF471KW01L.
3. Board/ground plane size has been minimized. This
reduces the dipole antenna formed between the logic
side and isolated side ground planes.
4. Top signal routing and ground floods have been opti-
mized to reduce signal loops, minimizing differential
mode radiation.
5. Common mode filtering is integrated into the input and
output pin headers. Filtering helps to reduce emissions
caused by conducted noise and minimizes the effects
of cabling to common mode emissions.
6. A combination of low ESL and high ESR decoupling is
used. A low ESL ceramic capacitor is located close to
the module minimizing high frequency noise conduction.
A high ESR tantalum capacitor is included to minimize
board resonances and prevent voltage spikes due to
hot plugging of the supply voltage.
EMI performance is shown in Figure 1, measured using
a Gigahertz Transverse Electromagnetic (GTEM) cell and
method detailed in IEC 61000-4-20, “Testing and Mea-
surement Techniques – Emission and Immunity Testing
in Transverse Electromagnetic Waveguides”.
