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dc1760af
DEMO MANUAL DC1760A
QUICK START PROCEDURE
Applying Power and Signals To The FT996
Demonstration Circuit
If a DC890 is used to acquire data from the DC1760A, the
DC890 must
first
be connected to a powered USB port
or provided an external 6V to 9V
before
applying 3.0V to
6.0V across the pins 3.3V and GND, or 2.7V to
3.5V on the V_AMP pin on the DC1760A. The DC1760A
requires 3.3V on the ADC input for proper operation,
regulators on the board produce the voltages required
for the ADC. The voltage applied to the amplifier is not
regulated. The DC1760A demonstration circuit requires
up to 150mA on the ADC input depending on the sampling
rate and the A/D converter supplied, and up to 25mA on
the amplifier power input.
The DC890 data collection board is powered by the USB
cable and does not require an external power supply unless
it must be connected to the PC through an unpowered hub
in which case it must be supplied an external 6V to 9V on
turrets G7(+) and G1(–) or the adjacent 2.1mm power jack.
Analog Input Network
The DC1760A can be driven from a differential or single-
ended source. If the DC1760A is driven from a single-ended
source applied to the AIN+ connector (J8), the equivalent
impedance characteristic should be seen on the AIN–
connector (J9). If there is a difference in the impedance
characteristic between the two input ports common mode
noise sources in the amplifier will translate to differential
mode noise and will raise the noise floor.
For optimal distortion and noise performance the filter
network can be optimized for different analog input fre-
quencies. Refer to the LTC6409 data sheet for information
on setting the gain and input impedance of the LTC6409.
In almost all cases, filters will be required on both analog
input and encode clock to produce maximum SNR. In the
case of the DC1760A the bandpass filter used for the clock
should be used prior to the DC1075A clock divide board.
The filters should be located close to the inputs to avoid
reflections from impedance discontinuities at the driven
end of a long transmission line. Most filters do not present
50Ω outside the passband. In some cases, 3dB to 10dB
pads may be required to obtain low distortion.
Encode Clock
Note: Apply an encode clock to the SMA connector on
the DC1760A demonstration circuit board marked J7.
As a default the DC1760A is populated to have a single-
ended input.
For the best noise performance, the encode input must
be driven with a very low jitter, square wave source. The
amplitude should be large, up to 3V
P-P
or 13dBm. When
using a sinusoidal signal generator a squaring circuit can
be used. Linear Technology also provides demo board
DC1075A that divides a high frequency sine wave by four,
producing a low jitter square wave for best results with
the LTC2261-14 ADC family.
Using bandpass filters on the clock and the analog input
will improve the noise performance by reducing the
wideband noise power of the signals. In the case of the
DC1760A a bandpass filter used for the clock should be
used prior to the DC1075A. Data sheet FFT plots are taken
with 10-pole LC filters made by TTE (Los Angeles, CA) to
suppress signal generator harmonics, non-harmonically
related spurs and broadband noise. Low phase noise Agilent
8644B generators are used with TTE bandpass filters for
both the clock input and the analog input.
Apply the analog input signal of interest to the SMA connec-
tors on the DC1760A demonstration circuit board marked
J5 and J3. This combo board is currently populated to
receive a differential signal.
An internally generated conversion clock output is available
on J1 which could be collected via a logic analyzer, or other
data collection system if populated with a SAMTEC MEC8-
150 type connector or collected by the DC890 QuikEval-II
Data Acquisition Board using PScope™ software.
