1
dc1760af
DEMO MANUAL DC1760A
DESCRIPTION
LTC2261-14 and LTC6409
12-/14-Bit, 25Msps to 150Msps
ADC Combo Board
Demonstration circuit 1760A supports a family of 14-
/12-bit 25Msps to 150Msps ADCs and an LTC
®
6409 low
noise amplifier. Each assembly features a device from the
LTC2261-14 family of high dynamic range 1.8V ADCs and
a LTC6409 low noise amplifier.
Demonstration circuit 1760A supports the LTC2261-14
family full rate CMOS and DDR CMOS output mode. The
L
, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and PScope
and QuikEval are trademarks of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
PERFORMANCE SUMMARY
(T
A
= 25°C)
circuitry on the analog inputs is optimized for analog input
frequencies from DC to 100MHz. Refer to the data sheet
for proper input networks for different input frequencies.
Design files for this circuit board are available at
http://www.linear.com/demo
PARAMETER
CONDITION
VALUE
Supply Voltage—ADC
Depending on Sampling Rate and the A/D
Converter Provided, This Supply Must Provide Up
to 150mA
Optimized for 3.3V [3.0V
⇔
3.5V Min/Max]
Supply Voltage—Amplifier
Depending on Supply Voltage Used, This Supply
Must Provide Up to 25mA
Optimized for 3.0V [2.7V
⇔
5.0V Min/Max]
Analog Input Range
Depending On Sense Pin Voltage
1V
P-P
to 2V
P-P
Logic Input Voltages
Minimum Logic High
1.3V
Maximum Logic Low
0.6V
Logic Output Voltages (OV
DD
= 1.8V)
Minimum High Level Output Voltage
1.750V (1.790V Typical)
Maximum Low Level Output Voltage
0.050V (0.010V Typical)
Sampling Frequency (Convert Clock Frequency)
Depending on ADC This Can Vary Between
20Msps and 125Msps
LTC2261-14 = 125Msps
Convert Clock Level
Single-Ended Encode Mode (ENC
–
Tied To Gnd)
0V to 3.6V
Convert Clock Level
Differential Encode Mode (ENC
–
Not Tied to GND) 0.2V to 3.6V
Resolution
14 Bits
Input Frequency Range
DC-100MHz
SFDR
See Applicable Data Sheet
SNR
See Applicable Data Sheet
