LTM4622A
23
Rev B
APPLICATIONS INFORMATION
Figure 26. Recommended PCB Layout
LAYOUT CHECKLIST/EXAMPLE
The high integration of LTM4622A makes the PCB board
layout very simple and easy. However, to optimize its
electrical and thermal performance, some layout con-
siderations are still necessary.
• Use large PCB copper areas for high current paths,
including V
IN1
, V
IN2
, GND, V
OUT1
and V
OUT2
. It helps
to minimize the PCB conduction loss and thermal
stress.
• Place high frequency ceramic input and output capaci-
tors next to the V
IN
, PGND and V
OUT
pins to minimize
high frequency noise.
• Place a dedicated power ground layer underneath
the unit.
• The two dedicated input decoupling capacitors, one for
each V
IN
, closely placed on each side of the module.
• To minimize the via conduction loss and reduce module
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
• Do not put via directly on the pad, unless they are
capped or plated over.
• Use a separated SGND ground copper area for com-
ponents connected to signal pins. Connect the SGND
to GND underneath the unit.
• For parallel modules, tie the V
OUT
, V
FB
, and COMP pins
together. Use an internal layer to closely connect these
pins together. The TRACK pin can be tied a common
capacitor for regulator soft-start.
• Bring out test points on the signal pins for monitoring.
Figure 26 gives a good example of the recommended layout.
4622A F26
GND
V
OUT2
V
OUT1
V
IN2
V
IN1
