Lime Microsystems LMS7002M Series Programming And Calibration Manual Download Page 62

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Address (15 bits)

Bits

Description

0x009D

15 – 8

7 – 0

RDIV_RXBUF[7:0]:Controls the output voltage of the LDO by setting the resistive
voltage divider ratio.

Default: 101

Vout=860mV+3.92mV *RDIV

RDIV_TBB[7:0]:Controls the output voltage of the LDO by setting the resistive
voltage divider ratio.

Default: 101

Vout=860mV+3.92mV *RDIV

Default

: 01100101 01100101

0x009E

15 – 8

7 – 0

RDIV_MXRFE[7:0]:Controls the output voltage of the LDO by setting the resistive
voltage divider ratio.

Default: 101

Vout=860mV+3.92mV *RDIV

RDIV_RBB[7:0]:Controls the output voltage of the LDO by setting the resistive
voltage divider ratio.

Default: 140

Vout=860mV+3.92mV *RDIV

Default

: 01100101 10001100

0x009F

15 – 8

7 – 0

RDIV_LNA12[7:0]:Controls the output voltage of the LDO by setting the resistive
voltage divider ratio.

Default: 101

Vout=860mV+3.92mV *RDIV

RDIV_LNA14[7:0]:Controls the output voltage of the LDO by setting the resistive
voltage divider ratio.

Default: 140

Vout=860mV+3.92mV *RDIV

Default

: 01100101 10001100

0x00A0

15 – 8

7 – 0

RDIV_DIVSXR[7:0]:Controls the output voltage of the LDO by setting the resistive
voltage divider ratio.

Default: 101

Vout=860mV+3.92mV *RDIV

RDIV_DIVSXT[7:0]:Controls the output voltage of the LDO by setting the resistive
voltage divider ratio.

Default: 101

Vout=860mV+3.92mV *RDIV

Default

: 01100101 01100101

0x00A1

15 – 8

7 – 0

RDIV_DIGSXT[7:0]:Controls the output voltage of the LDO by setting the resistive
voltage divider ratio.

Default: 101

Vout=860mV+3.92mV *RDIV

RDIV_DIVGN[7:0]:Controls the output voltage of the LDO by setting the resistive
voltage divider ratio.

Default: 101

Vout=860mV+3.92mV *RDIV

Default

: 01100101 01100101

0x00A2

15 – 8

7 – 0

RDIV_DIGGN[7:0]:Controls the output voltage of the LDO by setting the resistive
voltage divider ratio.

Default: 101

Vout=860mV+3.92mV *RDIV

RDIV_DIGSXR[7:0]:Controls the output voltage of the LDO by setting the resistive
voltage divider ratio.

Default: 101

Vout=860mV+3.92mV *RDIV

Default

: 01100101 01100101

0x00A3

15 – 8

7 – 0

RDIV_CPSXT[7:0]:Controls the output voltage of the LDO by setting the resistive
voltage divider ratio.

Default: 101

Vout=860mV+3.92mV *RDIV

RDIV_DIG[7:0]:Controls the output voltage of the LDO by setting the resistive
voltage divider ratio.

Default: 101

Vout=860mV+3.92mV *RDIV

Default

: 01100101 01100101

0x00A4

15 – 8

7 – 0

RDIV_CPGN[7:0]:Controls the output voltage of the LDO by setting the resistive
voltage divider ratio.

Default: 101

Vout=860mV+3.92mV *RDIV

RDIV_CPSXR[7:0]:Controls the output voltage of the LDO by setting the resistive
voltage divider ratio.

Default: 101

Vout=860mV+3.92mV *RDIV

Default

: 01100101 01100101

0x00A5

15 – 8

7 – 0

RDIV_SPIBUF[7:0]:Controls the output voltage of the LDO by setting the resistive
voltage divider ratio.

Default: 101

Vout=860mV+3.92mV *RDIV

RDIV_AFE[7:0]:Controls the output voltage of the LDO by setting the resistive
voltage divider ratio.

Default: 101

Vout=860mV+3.92mV *RDIV

Default

: 01100101 01100101

Summary of Contents for LMS7002M Series

Page 1: ...ildford Surrey GU2 7YG United Kingdom Tel 44 0 1483 685 063 Fax 44 0 1428 656 662 e mail enquiries limemicro com LMS7002M Multi Band Multi Standard MIMO RF Transceiver IC Programming and Calibration Guide Chip version LMS7002M Mask revision 01 Document version 3 01 Document revision 4 ...

Page 2: ......

Page 3: ...ation Memory 50 2 18 LDO Configuration Memory 51 2 19 EN_DIR Configuration Memory 60 2 20 SXR SXT and CGEN BIST Configuration Memory 61 2 21 CDS Configuration Memory 62 2 22 mSPI Configuration Memory 64 2 23 DC Calibration Configuration Memory 65 2 24 RSSI PDET and TEMP measurement Configuration Memory 70 2 25 Analog RSSI Calibration Configuration Memory 72 3 SPI Procedures 73 A1 1 SPI READ WRITE ...

Page 4: ...2 Main resistor bias calibration 102 A3 3 RBB calibration 104 A3 3 1 RBB Low Band Calibration 104 A3 3 2 RBB High band Calibration 106 A3 4 Nested algorithms 107 A3 4 1 Algorithm A 107 A3 4 2 Algorithm B 107 A3 4 3 Algorithm F 109 A3 5 TBB calibration 111 A3 6 TBB Low Band Calibration 111 A3 7 TBB High Band Calibration 114 A3 8 Nested algorithms 115 A3 8 1 Algorithm A 115 A3 8 2 Algorithm B 115 A3...

Page 5: ...egister LML1_SISODDR added address 0x0022 12 Description of registers at addresses 0x0024 0x0027 updated Register name LML1_TX_PST changed to LML1_BB2RF_PST description updated address 0x0025 12 8 Register name LML1_TX_PRE changed to LML1_BB2RF_PRE description updated address 0x0025 4 0 Register name LML1_RX_PST changed to LML1_RF2BB_PST description updated address 0x0026 12 8 Register name LML1_R...

Page 6: ...ddress 0x040C 8 Version 31r01 Released 6 Mar 2017 Register DCLOOP_BYP address 0x040C 8 renamed to DCLOOP_STOP description changed Version 31r02 Released 27 Mar 2017 New register TRX_GAIN_SRC added address 0x0081 15 New chapter 2 12 with new registers at addresses 0x0125 and 0x0126 added MASK register default value updated Version 31r03 Released 03 Aprl 2017 Figure 19 updated pin naming corrected t...

Page 7: ...ed on the clock s rising edge while data is shifted on the clock s falling edge i e clock polarity CPOL 0 and clock phase CPHA 0 32 serial clock cycles are required to complete write operation 32 serial clock cycles are required to complete read operation Multiple write read operations are possible without toggling serial enable signal All configuration registers are 16 bit wide Write read sequenc...

Page 8: ...A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Write instruction Data Don t care Don t care tES tDS tDH tEH Figure 1 SPI write cycle 3 wire and 4 wire modes SCLK Don t care SEN SDIO Don t care A14 0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Read instruction Don t care Don t care tES tDS tDH tEH SDO Don t care Output Data D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Don t ...

Page 9: ...ed in Table 1 To save the addressing space and speed up write operation the following trick is used for the TRX TX and RX logical block types There is a register called MAC 1 0 address of this register is 0x0020 1 0 which selects MIMO channel A or and B MIMO channel select logic depends on MAC 1 0 register as described below see Figure 1 for reference 11 SPI write operation possible only The same ...

Page 10: ...AC 1 0 to 10 The special case is frequency synthesizers SXR and SXT Register addresses are the same for SXR and SXT To control SXT we have to set MAC 1 0 to the 10 and MAC 1 0 to the 01 for SXR Modules from the Top and Other logical blocks see Table 1 are not controlled by the MAC 1 0 register TRXA Block TXA Block RXA Block TRXB Block TXB Block RXB Block Top Block Other Block SPI Bus MAC 0 MAC 1 M...

Page 11: ...0 Selected MIMO channel depends on MAC 1 0 TxGFIR1 A B 64 0 1 0000 01010 xxxxxx Address space starts at 0x0280 Selected MIMO channel depends on MAC 1 0 TxGFIR2 A B 64 0 1 0000 01011 xxxxxx Address space starts at 0x02C0 Selected MIMO channel depends on MAC 1 0 TxGFIR3a A B 64 0 1 0000 01100 xxxxxx Address space starts at 0x0300 Selected MIMO channel depends on MAC 1 0 TxGFIR3b A B 64 0 1 0000 0110...

Page 12: ...is possible to control the drive strength and pull up resistor value of each IO cell The tables in this chapter describe the control registers of the IO cells and LimeLightTM Ports 1 and 2 The control diagram of the LimeLightTM ports is shown in Figure 27 The general purpose control registers are also described in this chapter ...

Page 13: ...esets all the logic registers to the default state for Rx MIMO channel A 0 Reset active 1 Reset inactive default MRST_RX_A Resets all the configuration memory to the default state for Rx MIMO channel A 0 Reset active 1 Reset inactive default SRST_RXFIFO RX FIFO soft reset LimeLightTM Interface 0 Reset active 1 Reset inactive default SRST_TXFIFO TX FIFO soft reset LimeLightTM Interface 0 Reset acti...

Page 14: ...CL pad 0 Pull up disengaged 1 Pull up engaged default SCL_DS Driver strength of SCL pad 0 Driver strength is 4mA default 1 Driver strength is 8mA SDIO_DS Driver strength of SDIO pad 0 Driver strength is 4mA default 1 Driver strength is 8mA SDIO_PE Pull up control of SDIO pad 0 Pull up disengaged 1 Pull up engaged default SDO_PE Pull up control of SDO pad 0 Pull up disengaged 1 Pull up engaged defa...

Page 15: ...p control of IQ_SEL_EN_2 pad 0 Pull up disengaged 1 Pull up engaged default TXNRX2_PE Pull up control of TXNRX2 pad 0 Pull up disengaged 1 Pull up engaged default FCLK2_PE Pull up control of FCLK2 pad 0 Pull up disengaged 1 Pull up engaged default MCLK2_PE Pull up control of MCLK2 pad 0 Pull up disengaged 1 Pull up engaged default DIQ1_DS Driver strength of DIQ1 pad 0 Driver strength is 4mA defaul...

Page 16: ... controllable from ENABLEDIR1 ENABLEDIR1 ENABLE1 direction 0 Output 1 Input default Reserved MOD_EN LimeLightTM interface enable 0 Interface disabled 1 Interface enabled default LML2_FIDM Frame start ID selection for Port 2 when LML2_MODE 0 0 Frame start when 0 default 1 Frame start when 1 LML2_RXNTXIQ TXIQ RXIQ mode selection for Port 2 when LML2_MODE 0 0 BB2RF TXIQ mode 1 RF2BB RXIQ mode default...

Page 17: ... 1 is BB2RF 11 BI sample position is 3 10 BI sample position is 2 default 01 BI sample position is 1 00 BI sample position is 0 LML1_AQP 1 0 AQ sample position in frame when direction of Port 1 is BB2RF 11 AQ sample position is 3 10 AQ sample position is 2 01 AQ sample position is 1 default 00 AQ sample position is 0 LML1_AIP 1 0 AI sample position in frame when direction of Port 1 is BB2RF 11 AI ...

Page 18: ... is BB2RF 11 BI sample position is 3 10 BI sample position is 2 default 01 BI sample position is 1 00 BI sample position is 0 LML2_AQP 1 0 AQ sample position in frame when direction of Port 2 is BB2RF 11 AQ sample position is 3 10 AQ sample position is 2 01 AQ sample position is 1 default 00 AQ sample position is 0 LML2_AIP 1 0 AI sample position in frame when direction of Port 2 is BB2RF 11 AI sa...

Page 19: ...e is Port 2 00 Data source is Port 1 default TXRDCLK_MUX 1 0 TX FIFO read clock selection 10 11 Clock source is TxTSPCLK default 01 Clock source is FCLK2 00 Clock source is FCLK1 TXWRCLK_MUX 1 0 TX FIFO write clock selection 10 11 Clock source is RxTSPCLK use for TSP loop back 01 Clock source is FCLK2 00 Clock source is FCLK1 default RXRDCLK_MUX 1 0 RX FIFO read clock selection 11 Clock source is ...

Page 20: ... divider enable 1 Divider enabled 0 Divider disabled default RXDIVEN RX clock divider enable 1 Divider enabled 0 Divider disabled default Default 00000000 00010000 0x002C 15 8 7 0 TXTSPCLKA_DIV 7 0 TxTSP clock divider used to produce MCLK 1 2 clocks Clock division ratio is 2 TXTSPCLKA_DIV 1 Unsigned integer Possible values are 0 255 default is 255 RXTSPCLKA_DIV 7 0 RxTSP clock divider used to prod...

Page 21: ...elects PHO or FCW to feed to NCO according to MODE Shadow register 0000 PHO0 or FCW0 selected default 0001 PHO1 or FCW1 selected 1111 PHO15 or FCW15 selected MODE Memory table mode Shadow register 1 PHO table data at addresses 0x4 to 0x13 are PHO 0 FCW table data at addresses 0x2 to 0x20 are FCW default Default 00000000 00100000 TX A B 0x0241 RX A B 0x0441 15 0 PHO 15 0 NCO Phase offset register w...

Page 22: ...NCO Phase offset register 9 when MODE 1 Default 00000000 00000000 TX A B 0x024E RX A B 0x044E 15 0 FCW6 31 16 NCO frequency control word register 6 when MODE 0 MSB part PHO10 15 0 NCO Phase offset register 10 when MODE 1 Default 00000000 00000000 TX A B 0x024F RX A B 0x044F 15 0 FCW6 15 0 NCO frequency control word register 6 when MODE 0 LSB part PHO11 15 0 NCO Phase offset register 11 when MODE 1...

Page 23: ...rved when MODE 1 Default 00000000 00000000 TX A B 0x025C RX A B 0x045C 15 0 FCW13 31 16 NCO frequency control word register 13 when MODE 0 MSB part Reserved when MODE 1 Default 00000000 00000000 TX A B 0x025D RX A B 0x045D 15 0 FCW13 15 0 NCO frequency control word register 13 when MODE 0 LSB part Reserved when MODE 1 Default 00000000 00000000 TX A B 0x025E RX A B 0x045E 15 0 FCW14 31 16 NCO frequ...

Page 24: ...Do not swap default 1 Swap I an Q signal sources comming from TSG TSGMODE Test signal generator mode 0 NCO default 1 DC source INSEL Input source of TxTSP 0 LML output default 1 Test signal generator BSTART Starts TxTSP built in self test Keep it at 1 one at least three clock cycles 0 default 0 to 1 positive edge activates BIST EN TxTSP modules enable 0 Disabled 1 Enabled default Default 00000000 ...

Page 25: ...10 8 7 0 Reserved GFIR3_L 2 0 Parameter l of GFIR3 l roundUp CoeffN 15 1 Unsigned integer Possible values are 0 to 7 default is 0 GFIR3_N 7 0 Clock division ratio of GFIR3 is GFIR3_N 1 Unsigned integer Possible values are 0 to 255 default is 0 Default 00000000 00000000 0x0208 15 14 13 12 11 9 8 7 6 5 4 3 2 1 0 CMIX_GAIN 1 0 Gain of CMIX output least significant part CMIX_GAIN 2 CMIX_GAIN 1 0 CMIX ...

Page 26: ...nning 1 BIST in progress Read only 0x020A 15 8 7 0 BSIGQ 7 0 TxTSP BIST signature channel Q LSB BSIGI 22 15 TxTSP BIST signature channel I MSB Read only 0x020B 15 14 0 Reserved BSIGQ 22 8 TxTSP BIST signature channel Q MSB Read only 0x020C 15 0 DC_REG 15 0 DC data source for test purposes Possible values 2 16 1 0 default Default 00000000 00000000 ...

Page 27: ... Set frequency of TSG s NCO DC TSG NCO frequency 00 do not use 01 TSP clk 8 default 10 TSP clk 4 11 do not use TSGDCLDQ Load TSG DC Q register with value from DC_REG 15 0 0 No action default 0 to 1 positive edge loads TSG s DC register Q TSGDCLDI Load TSG DC I register with value from DC_REG 15 0 0 No action default 0 to 1 positive edge loads TSG s DC register I TSGSWAPIQ Swap signals at test sign...

Page 28: ...are 0 to 255 default is 0 Default 00000000 00000000 0x0406 15 11 10 8 7 0 Reserved GFIR2_L 2 0 Parameter l of GFIR2 l roundUp CoeffN 5 1 Unsigned integer Possible values are 0 to 7 default is 0 GFIR2_N 7 0 Clock division ratio of GFIR2 is GFIR2_N 1 Unsigned integer Possible values are 0 to 255 default is 0 Default 00000000 00000000 0x0407 15 11 10 8 7 0 Reserved GFIR3_L 2 0 Parameter l of GFIR3 l ...

Page 29: ...ive default AGC_BYP AGC bypass 1 Bypass 0 Use default GFIR3_BYP GFIR3 bypass 1 Bypass 0 Use default GFIR2_BYP GFIR2 bypass 1 Bypass 0 Use default GFIR1_BYP GFIR1 bypass 1 Bypass 0 Use default DC_BYP DC corrector bypass 1 Bypass 0 Use default GC_BYP Gain corrector bypass 1 Bypass 0 Use default PH_BYP Phase corrector bypass 1 Bypass 0 Use default Default 00000000 00000000 0x040E and 0x040F 15 8 7 0 ...

Page 30: ...xGFIR1 RxGFIR1 Tx 0x02A0 0x02A7 Rx 0x04A0 0x04A7 8 x 16 Tx Rx 1CMB4 7 0 15 0 Coefficients memory bank 4 for TxGFIR1 RxGFIR1 Tx 0x02A8 0x02BF Rx 0x04A8 0x04BF 24 x 16 Reserved Table 7 Memory space used to store TxGFIR2 RxGFIR2 coefficients Address 15 bits Bits Description Tx 0x02C0 0x02C7 Rx 0x04C0 0x04C7 8 x 16 Tx Rx 2CMB0 7 0 15 0 Coefficients memory bank 0 for TxGFIR2 RxGFIR2 Tx 0x02C8 0x02CF Rx...

Page 31: ...or TxGFIR2 RxGFIR3 Tx 0x0348 0x034F Rx 0x0548 0x054F 8 x 16 Tx Rx 3CMB1b 7 0 15 0 Coefficients memory bank 1b for TxGFIR2 RxGFIR3 Tx 0x0350 0x0357 Rx 0x0550 0x0557 8 x 16 Tx Rx 3CMB2b 7 0 15 0 Coefficients memory bank 2b for TxGFIR2 RxGFIR3 Tx 0x0358 0x035F Rx 0x0558 0x055F 8 x 16 Tx Rx 3CMB3b 7 0 15 0 Coefficients memory bank 3b for TxGFIR2 RxGFIR3 Tx 0x0360 0x0367 Rx 0x0560 0x0567 8 x 16 Tx Rx 3...

Page 32: ... for RXFE loopback 1 0 block active 1 block powered down default PD_RLOOPB_2_RFE_ 1 2 Power control signal for RXFE loopback 2 0 block active 1 block powered down default PD_MXLOBUF_RFE_ 1 2 Power control signal for RXFE mixer lo buffer 0 block active 1 block powered down default PD_QGEN_RFE_ 1 2 Power control signal for RXFE quadrature LO generator 0 block active 1 block powered down default PD_R...

Page 33: ...AW Switch ON resistance 3ohm 0 switch OFF 1 switch ON default Should be 1 when LNAW is NOT active EN_NEXTRX_RFE_ 1 2 Enables the daisy chain LO buffer going from RXFE1 to RXFE2 0 SISO default 1 MIMO Default 00000000 10011110 0x010E 15 14 13 7 6 0 Reserved DCOFFI_RFE_ 1 2 6 0 Controls DC offset at the output of the TIA by injecting current to the input of the TIA for I side Default 64 DCOFFSETx_RFE...

Page 34: ...output of the RX Mixer Default 4 SE cap CAP_RXMXO_RFE 1 80fF CGSIN_LNA_RFE_ 1 2 4 0 Controls the cap parallel with the LNA input NMOS CGS to control the Q of the matching circuit and provides trade off between gain NF and IIP The higher the frequency the lower CGSIN_LNA_RFE should be Also the higher CGSIN the lower the Q The lower the gain the higher the NF and the higher the IIP3 0 for 3500MHz 1 ...

Page 35: ... Gmax 6 2 6 Gmax 7 5 5 Gmax 9 4 Gmax 11 3 Gmax 14 2 Gmax 17 1 Gmax 24 0 Gmax 40 default Should be 0 when actual LNAs are working G_TIA_RFE_ 1 2 1 0 Controls the Gain of the TIA 3 Gmax default 2 Gmax 3 1 Gmax 12 0 Not allowed Default 00000011 11000011 0x0114 15 9 8 5 4 0 Reserved RCOMP_TIA_RFE_ 1 2 3 0 Controls the compensation resistors of the TIA operational amplifier 11 for CFB 220 4 default 5 f...

Page 36: ...ered down default PD_LPFL_RBB_ 1 2 Power down of the LPFL block 0 active default 1 powered down PD_PGA_RBB_ 1 2 Power down of the PGA block 0 active default 1 powered down EN_G_RBB_ 1 2 Enable control for all the RBB_1 power downs 0 All RBB modules powered down 1 All RBB modules controlled by individual power down registers default Default 00000000 00001001 0x0116 15 11 10 8 7 0 R_CTL_LPF_RBB_ 1 2...

Page 37: ...rational amplifier used in RBB_LPF blocks Low or High Must increase up to 24 when a strong close blocker is detected to maintain the linearity performance Default 12 ICT_LPF_OUT_RBB_ 1 2 4 0 Controls the reference bias current of the output stage of the operational amplifier used in RBB_LPF blocks low or High Must increase up to 24 when a strong close blocker is detected to maintain the linearity ...

Page 38: ...n offline off chip lookup table can be generated and stored Default 23 Reserved C_CTL_PGA_RBB_ 1 2 7 0 Control the value of the feedback capacitor of the PGA that is used to help against the parasitic cap at the virtual node for stability 3 when 0 G_PGA_RBB 8 2 when 8 G_PGA_RBB 13 default 1 when 13 G_PGA_RBB 21 0 when 21 G_PGA_RBB Default 00101110 00000010 0x011B 15 7 6 0 Reserved RESRV_RBB_ 1 2 6...

Page 39: ...Detector 0 Enabled 1 Powered down default PD_TLOBUF_TRF_ 1 2 Power down signal for TX LO buffer 0 Enabled default 1 Powered down PD_TXPAD_TRF_ 1 2 Power down signal for TXPAD 0 Enabled default 1 Powered down EN_G_TRF_ 1 2 Enable control for all the TRF_1 power downs 0 All TRF_1 modules powered down 1 All TRF_1 modules controlled by individual power down registers default Default 00110100 00001001 ...

Page 40: ...D 12 100u 10K when GCAS_GNDREF 1 vgcas VDD18 VGCAS_TXOAD 12 100u 7 5K when GCAS_GNDREF 0 Default 00110001 10000000 0x0103 15 12 11 10 9 5 4 0 Reserved SEL_BAND1_TRF_ 1 2 Enable signal for TXFE band 1 0 Disabled 1 Enabled default SEL_BAND2_TRF_ 1 2 Enable signal for TXFE band 2 0 Disabled default 1 Enabled LOBIASN_TXM_TRF_ 1 2 4 0 Controls the bias at the gate of the mixer NMOS switch Default 16 Vg...

Page 41: ... to the loopb outputs on setting 3 Reserved PD_LPFH_TBB_ 1 2 This selectively powers down the LPFH_TBB biquad Please note the LPFH_TBB is powered down if any of the following is true PD_LPFLAB_TBB 0 PD_LPFS5_TBB 0 or PD_TBB 1 or PD_LPFH_TBB 1 0 Active default 1 powered down PD_LPFIAMP_TBB_ 1 2 This selectively powers down the LPFIAMP_TBB front end current amp of the transmitter base band Please no...

Page 42: ... For a given gain value this control value varies with the set TX mode After resistance calibration the following table gives the nominal values for each frequency setting However this table is to be updated and corrected after calibration Default 37 Low Band 5 when 2 4MHz 7 when 2 74MHz 12 when 5 5MHz 18 when 8 2MHz 24 when 11MHz High Band 18 when 18 5MHz 37 when 38MHz 54 when 54MHz ICT_IAMP_FRP_...

Page 43: ...he banks equivalent capacitor to their respective nominal values Default 16 RCAL_LPFS5_TBB_ 1 2 7 0 This controls the value of the equivalent resistance of the resistor banks of the real pole filter stage of the low band section of the transmitter base band TBB Following is a nominal values table that are corrected for any process variation after calibration If 5 5MHz 200 otherwise 76 Default 76 D...

Page 44: ...4 0 Controls the gain output power of the TXPAD Default 0 0 Loss 10 Pout Pout_max Loss 11 Loss 31 Pout Pout_max 10 2 Loss 10 Default 10010100 00000000 0x0126 15 13 12 11 10 6 5 2 1 0 Reserved C_CTL_PGA_RBB_ 1 2 7 0 Control the value of the feedback capacitor of the PGA that is used to help against the parasitic cap at the virtual node for stability 3 when 0 G_PGA_RBB 8 2 when 8 G_PGA_RBB 13 defaul...

Page 45: ...T 1 0 3 RSSI 1 output will be connected to ADC 1 input MUX_AFE_2 1 0 Controls the MUX at the input of the ADC channel 2 0 MUX off only PGA output is connected to ADC input default 1 pdet_2 is connected to ADC channel 2 PGA should be powered down 2 RSSI 1 output will be connected to ADC 2 input 3 RSSI 2 output will be connected to ADC 2 input Reserved PD_AFE Power down control for the AFE current m...

Page 46: ... and RP_CALIB_BIAS is changed until vr_ext becomes 600mV 2 Vptat_600mV and vr_cal_ref 600mV is passed to the ADC input MUX The ratio between the two will be proportional to absolute temp 3 No test mode RP_CALIB_BIAS 4 0 Calibration code for rppolywo This code is set by the calibration algorithm BIAS_RPPOLY_calibration Default 16 Reserved PD_FRP_BIAS Power down signal for Fix RP block 0 Enabled def...

Page 47: ...vider works up to 5 5GHz For FVCO 5 5GHz the prescaler is needed to lower the input frequency to DIVPROG_SX Shadow register 0 DIVPROG input Fvco Fvco Fref INT_SDM_SX 4 FRAC_SDM 1 DIVPROG input Fvco 2 Fvco 2 Fref INT_SDM_SX 4 FRAC_SDM default EN_INTONLY_SDM_ SXR SXT Enables INTEGER N mode of the SX 0 Frac N mode default 1 INT N mode EN_SDM_CLK_ SXR SXT Enables Disables SDM clock In INT N mode or fo...

Page 48: ...dow register Default 1 TST_SX_ SXR SXT 2 0 Controls the test mode of PLLs TST signal lines are shared between all PLLs CGEN RX and TX Only one TST signal of any PLL should be active at a given time 0 TST disabled RSSI analog outputs enabled if RSSI blocks active and when all PLL test signals are off default 1 tstdo 0 VCO 20 clock tstdo 1 VCO 40 clock tstao High impedance 2 tstdo 0 SDM clock tstdo ...

Page 49: ...lses of PFD It can be used to reverse the polarity of the PLL loop positive feedback to negative feedback Default 0 IOFFSET_CP_ SXR SXT 5 0 Scales the offset current of the charge pump 0 63 This current is used in Fran N mode to create an offset in the CP response and avoid the non linear section Default 20 ioffset 0 243uA IOFFSET_CP_SX ioffset ipulse 4 INT_SDM_SX 4 First estimation IPULSE_CP_ SXR...

Page 50: ...t control of PDs and ENs for RBB 1 2 module 0 direct control disabled default 1 direct control enabled EN_DIR_RFE 1 2 Enables direct control of PDs and ENs for RFE 1 2 module 0 direct control disabled default 1 direct control enabled EN_DIR_TBB 1 2 Enables direct control of PDs and ENs for TBB 1 2 module 0 direct control disabled default 1 direct control enabled EN_DIR_TRF 1 2 Enables direct contr...

Page 51: ...mode default 1 INT N mode EN_SDM_CLK_CGEN Enables Disables SDM clock In INT N mode or for noise testing SDM clock can be disabled 0 SDM clock disabled 1 SDM clock enabled default Reserved PD_CP_CGEN Power down for Charge Pump 0 block active default 1 block powered down PD_FDIV_FB_CGEN Power down for feedback frequency divider 0 block active default 1 block powered down PD_FDIV_O_CGEN Power down fo...

Page 52: ... 60kOhm resistor 7 tstdo 0 High impedance tstdo 1 High impedance tstao VCO tune through a 10kOhm resistor if TST_SX 2 1 VCO_TSTBUF active generating VCO_TST_DIV20 and VCO_TST_DIV40 Default 00000000 00100000 0x008A 15 14 13 12 11 6 5 0 Reserved REV_CLKDAC_CGEN Inverts the clock F_CLKL 0 Normal default 1 Inverted REV_CLKADC_CGEN Inverts the clock F_CLKL 0 Normal default 1 Inverted REVPH_PFD_CGEN Rev...

Page 53: ...f CP2 cap from CP output to GND in the PLL filter Default 6 cp2 CP2_PLL_SX 6 63 2fF CP3_CGEN 3 0 Controls the value of CP3 cap from VCO Vtune input to GND in the PLL filter Default 7 cp3 CP3_PLL_SX 248fF CZ_CGEN 3 0 Controls the value of CZ Zero capacitor in the PLL filter Default 11 cz CZ_PLL_SX 8 365fF Default 00000110 01111011 0x008D 15 2 1 0 Reserved RESRV_CGN 2 1 Reserved Default 0 Default 00...

Page 54: ... input in Bypass mode should be a 1 2V full scale CMOS signal 0 Bypass not active default 1 Bypass active BYP_XBUF_TX Shorts the Input 3 3V buffer in XBUF The final 2 1 2V buffers are still active The input in Bypass mode should be a 1 2V full scale CMOS signal 0 Bypass not active default 1 Bypass active EN_OUT2_XBUF_TX Enables the 2nd output of TX XBUF This 2nd buffer goes to XBUF_RX This should ...

Page 55: ...DIVSXR Enables the LDO 0 Powered down default 1 Enabled EN_LDO_DIVSXT Enables the LDO 0 Powered down default 1 Enabled EN_LDO_LNA12 Enables the LDO 0 Powered down default 1 Enabled EN_LDO_LNA14 Enables the LDO 0 Powered down default 1 Enabled EN_LDO_MXRFE Enables the LDO 0 Powered down default 1 Enabled EN_LDO_RBB Enables the LDO 0 Powered down default 1 Enabled EN_LDO_RXBUF Enables the LDO 0 Powe...

Page 56: ...as to optimize the load regulation 0 Constant bias default 1 Load dependent bias EN_LOADIMP_LDO_VCOSXT Enables the load dependent bias to optimize the load regulation 0 Constant bias default 1 Load dependent bias EN_LDO_AFE Enables the LDO 0 Powered down default 1 Enabled EN_LDO_CPGN Enables the LDO 0 Powered down default 1 Enabled EN_LDO_CPSXR Enables the LDO 0 Powered down default 1 Enabled EN_L...

Page 57: ...EN_LOADIMP_LDO_DIVSXT Enables the load dependent bias to optimize the load regulation 0 Constant bias default 1 Load dependent bias EN_LOADIMP_LDO_LNA12 Enables the load dependent bias to optimize the load regulation 0 Constant bias default 1 Load dependent bias EN_LOADIMP_LDO_LNA14 Enables the load dependent bias to optimize the load regulation 0 Constant bias default 1 Load dependent bias EN_LOA...

Page 58: ...UF Bypass signal for the LDO 0 Does not bypass Normal LDO operation default 1 Bypasses LDO Connects Vinput to Voutput BYP_LDO_VCOGN Bypass signal for the LDO 0 Does not bypass Normal LDO operation default 1 Bypasses LDO Connects Vinput to Voutput BYP_LDO_VCOSXR Bypass signal for the LDO 0 Does not bypass Normal LDO operation default 1 Bypasses LDO Connects Vinput to Voutput BYP_LDO_VCOSXT Bypass s...

Page 59: ..._LDO_DIGSXT Bypass signal for the LDO 0 Does not bypass Normal LDO operation default 1 Bypasses LDO Connects Vinput to Voutput BYP_LDO_DIVGN Bypass signal for the LDO 0 Does not bypass Normal LDO operation default 1 Bypasses LDO Connects Vinput to Voutput BYP_LDO_DIVSXR Bypass signal for the LDO 0 Does not bypass Normal LDO operation default 1 Bypasses LDO Connects Vinput to Voutput BYP_LDO_DIVSXT...

Page 60: ...g time 0 noise filter resistor in place default 1 Noise filter resistor bypassed should be connected to a 1 5uS at the power up SPDUP_LDO_TIA12 Short the noise filter resistor to speed up the settling time 0 noise filter resistor in place default 1 Noise filter resistor bypassed should be connected to a 1 5uS at the power up SPDUP_LDO_TIA14 Short the noise filter resistor to speed up the settling ...

Page 61: ...DO_DIGSXT Short the noise filter resistor to speed up the settling time 0 noise filter resistor in place default 1 Noise filter resistor bypassed should be connected to a 1 5uS at the power up SPDUP_LDO_DIVGN Short the noise filter resistor to speed up the settling time 0 noise filter resistor in place default 1 Noise filter resistor bypassed should be connected to a 1 5uS at the power up Default ...

Page 62: ...ls the output voltage of the LDO by setting the resistive voltage divider ratio Default 101 Vout 860mV 3 92mV RDIV RDIV_DIVGN 7 0 Controls the output voltage of the LDO by setting the resistive voltage divider ratio Default 101 Vout 860mV 3 92mV RDIV Default 01100101 01100101 0x00A2 15 8 7 0 RDIV_DIGGN 7 0 Controls the output voltage of the LDO by setting the resistive voltage divider ratio Defaul...

Page 63: ...onnects Vinput to Voutput BYP_LDO_DIGIp1 Bypass signal for the LDO 0 Does not bypass Normal LDO operation default 1 Bypasses LDO Connects Vinput to Voutput EN_LOADIMP_LDO_SPIBUF Enables the load dependent bias to optimize the load regulation 0 Constant bias default 1 Load depdent bias EN_LOADIMP_LDO_DIGIp2 Enables the load dependent bias to optimize the load regulation 0 Constant bias default 1 Lo...

Page 64: ... combined registers Reserved EN_DIR_LDO Enables direct control of PDs and ENs for LDO module 0 direct control disabled default 1 direct control enabled EN_DIR_CGEN Enables direct control of PDs and ENs for CGEN module 0 direct control disabled default 1 direct control enabled EN_DIR_XBUF Enables direct control of PDs and ENs for XBUF module 0 direct control disabled default 1 direct control enable...

Page 65: ...DM_TSTO 12 0 outputs which will buffer the SDM outputs inputs to the frequency divider for testing purposes 0 all outputs are grounded default 1 SDM_TSTO active EN_SDM_TSTO_SXR Enables the SDM_TSTO 12 0 outputs which will buffer the SDM outputs inputs to the frequency divider for testing purposes 0 all outputs are grounded default 1 SDM_TSTO active EN_SDM_TSTO_CGEN Enables the SDM_TSTO 12 0 output...

Page 66: ...inversion control 0 Clock is inverted 1 Clock is not inverted default CDSN_RXBTSP RX TSPB clock inversion control 0 Clock is inverted 1 Clock is not inverted default CDSN_RXATSP RX TSPA clock inversion control 0 Clock is inverted 1 Clock is not inverted default CDSN_TXBLML TX LMLB clock inversion control 0 Clock is inverted 1 Clock is not inverted default CDSN_TXALML TX LMLA clock inversion contro...

Page 67: ...y by 1100ps CDS_RXATSP 1 0 RX TSP A clock delay 00 delay by 200ps default 01 delay by 500ps 10 delay by 800ps 11 delay by 1100ps CDS_TXBLML 1 0 TX LML B clock delay 00 delay by 400ps default 01 delay by 500ps 10 delay by 600ps 11 delay by 700ps CDS_TXALML 1 0 TX LML A clock delay 00 delay by 400ps default 01 delay by 500ps 10 delay by 600ps 11 delay by 700ps CDS_RXBLML 1 0 RX LML B clock delay 00 ...

Page 68: ...reading the EEPROM 0x0003 Reads MCU status signals mSPI_REG3 read only 15 8 7 6 5 4 3 2 1 0 Reserved TXD The USART transmit output pin PROGRAMMED Status output signal when is set it indicates that programming process is finished and MCU executes instructions Reserved READ_REQ status signal new 8 bit data the register mSPI_REG5 content is ready to be read through mSPI WRITE_REQ status signal a new ...

Page 69: ...PD_DCDAC_RXA Power down control for receiver channel A DC offset cancelation DAC 0 block active 1 block powered down default PD_DCDAC_TXB Power down control for transmiter channel B DC offset cancelation DAC 0 block active 1 block powered down default PD_DCDAC_TXA Power down control for transmitter channel A DC offset cancelation DAC 0 block active 1 block powered down default PD_DCCMP_RXB Power d...

Page 70: ...not running 1 Calibration is running DCCAL_CALSTATUS_TXAI TXAI DC calibration status Read only 0 Calibration is not running 1 Calibration is running DCCAL_CMPSTATUS_RXBQ RXBQ comparator value Used as status source for manual calibration routines Read only DCCAL_CMPSTATUS_RXBI RXBI comparator value Used as status source for manual calibration routines Read only DCCAL_CMPSTATUS_RXAQ RXAQ comparator ...

Page 71: ... calibration for RXBQ 0 to 1 Start automatic calibration DCCAL_START_RXBI Start automatic DC calibration for RXBI 0 to 1 Start automatic calibration DCCAL_START_RXAQ Start automatic DC calibration for RXAQ 0 to 1 Start automatic calibration DCCAL_START_RXAI Start automatic DC calibration for RXAI 0 to 1 Start automatic calibration DCCAL_START_TXBQ Start automatic DC calibration for TXBQ 0 to 1 Sta...

Page 72: ...ten to the as well as read value from TXBI DAC Default 0 DC_TXBI 10 sign DC_TXBI 9 0 magnitude Default 00000000 00000000 0x05C6 15 14 13 11 10 0 DCWR_TXBQ Used to enable manual write operation of TXBQ DAC values Value must be first stored in DC_TXBQ register prior to toggling this flag 0 to 1 writes the value to TXBQ DAC from DC_TXBQ register Default 0 DCRD_TXBQ Used to enable manual read operatio...

Page 73: ...fault 00000000 00000000 0x05CA 15 14 13 7 6 0 DCWR_RXBQ Used to enable manual write operation of RXBQ DAC values Value must be first stored in DC_RXBQ register prior to toggling this flag 0 to 1 writes the value to RXBQ DAC from DC_RXBQ register Default 0 DCRD_RXBQ Used to enable manual read operation of RXBQ DAC values 0 to 1 read the value from RXBQ DAC to DC_RXBQ register Default 0 Reserved DC_...

Page 74: ...ode is used for testing purposes 0 automatic default 1 manual MEASR_PD Power down the measurement modules 0 blocks active measurement enabled 1 blocks powered down measurement disabled default Default 00001111 00000001 0x0601 15 6 5 4 3 2 1 0 Reserved MEASR_CMPSTATUS_TREF Temperature Reference comparator value Read only MEASR_CMPSTATUS_TPTAT Temperature VPTAT comparator value Read only MEASR_CMPST...

Page 75: ...Comparator output inverted MEASR_CMPCFG_PDET2 Channel B analog peak detector in active TX path comparator configuration 0 Comparator output not inverted default 1 Comparator output inverted MEASR_CMPCFG_PDET1 Channel A analog peak detector in active TX path comparator configuration 0 Comparator output not inverted default 1 Comparator output inverted Default 00100000 00000000 0x0603 15 8 7 0 Reser...

Page 76: ...40 15 14 7 8 4 3 1 0 ARSSI_CMPSTATUS_ 1 2 Status of analog RSSI comparator Read Only Reserved ARSSI_RSEL_ 1 2 4 0 Reference voltage for the RSSI output comparator Voltage range 0 800mV 31 250mV approx values Default 10 Step size 0 to 4 50mV 5 to 12 21 5mV 13 to 31 10mV ARSSI_HYSCMP_ 1 2 2 0 Comparator hysteresis control for analog RSSI comparator 0 min hysteresis default 7 max hysteresis ARSSI_PD_...

Page 77: ...First 1 bit MSB Command Next 15 LSBs bits Register Address for int i 15 i 0 i if i th bit in COMMAND is 1 Set Data Output line to 1 else Set Data Output line to 0 Apply Rising and Falling CLK signal edges to CLK line Read Data MSB First Note At this point we have data MSB valid from the chip for int i 15 i 0 i if there is 1 at the Data Input Line Set i th bit in DATA 1 else Set i th bit in DATA 0 ...

Page 78: ...ATA Write Command Address for int i 15 i 0 i if i th bit in COMMAND is 1 Set Data Output line to 1 else Set Data Output line to 0 Apply Rising and Falling CLK signal edges to CLK line Write Data for int i 15 i 0 i if i th bit in DATA is 1 Set Data Output line to 1 else Set Data Output line to 0 Apply Rising and Falling CLK signal edges to CLK line ...

Page 79: ...75 A Ap pp pe en nd di ix x 2 2 Control Block Diagrams ...

Page 80: ...E_1 0x010C 3 SEL_PATH_RFE_1 0x010D 7 8 PD_RLOOPB_1_RFE_1 0x010C 6 EN_INSHSW_LB1_RFE_1 0x010D 4 G_RXLOOPB_RFE_1 0x0113 5 2 SEL_PATH_RFE_1 0x010D 7 8 PD_LNA_RFE_1 0x010C 7 CGSIN_LNA_RFE_1 0x0111 4 0 G_LNA_RFE_1 0x0113 9 6 EN_INSHSW_L_RFE_1 0x010D 2 SEL_PATH_RFE_1 0x010D 7 8 PD_LNA_RFE_1 0x010C 7 CGSIN_LNA_RFE_1 0x0111 4 0 G_LNA_RFE_1 0x0113 9 6 EN_INSHSW_W_RFE_1 0x010D 1 PD_RSSI_RFE_1 0x010C 2 CAP_R...

Page 81: ...2 0x010C 6 EN_INSHSW_LB1_RFE_2 0x010D 4 G_RXLOOPB_RFE_2 0x0113 5 2 SEL_PATH_RFE_2 0x010D 7 8 PD_LNA_RFE_2 0x010C 7 CGSIN_LNA_RFE_2 0x0111 4 0 G_LNA_RFE_2 0x0113 9 6 EN_INSHSW_L_RFE_2 0x010D 2 SEL_PATH_RFE_2 0x010D 7 8 PD_LNA_RFE_2 0x010C 7 CGSIN_LNA_RFE_2 0x0111 4 0 G_LNA_RFE_2 0x0113 9 6 EN_INSHSW_W_RFE_2 0x010D 1 CAP_RXMXO_RFE_2 0x0111 9 5 Analog signal lines Signal input output RESET_N XXXX IO ...

Page 82: ... 9 C_CTL_PGA_RBB_1 0x011A 7 0 OSW_PGA_RBB_1 0x0119 15 EN_LB_LPFL_RBB_1 0x0115 14 PD_LPFL_RBB_1 0x0115 2 R_CTL_LPF_RBB_1 0x0116 15 11 RCC_CTL_LPFL_RBB_1 0x0117 13 11 C_CTL_LPFL_RBB_1 0x0117 10 0 PD_PGA_RBB_1 0x0115 1 OSW_PGA_RBB_1 0x0119 15 RCC_CTL_PGA_RBB_1 0x011A 13 9 C_CTL_PGA_RBB_1 0x011A 7 0 PD_PGA_RBB_1 0x0115 1 OSW_PGA_RBB_1 0x0119 15 RCC_CTL_PGA_RBB_1 0x011A 13 9 C_CTL_PGA_RBB_1 0x011A 7 0 ...

Page 83: ...RBB_2 0x011A 7 0 OSW_PGA_RBB_2 0x0119 15 EN_LB_LPFL_RBB_2 0x0115 14 PD_LPFL_RBB_2 0x0115 2 R_CTL_LPF_RBB_2 0x0116 15 11 RCC_CTL_LPFL_RBB_2 0x0117 13 11 C_CTL_LPFL_RBB_2 0x0117 10 0 PD_PGA_RBB_2 0x0115 1 OSW_PGA_RBB_2 0x0119 15 RCC_CTL_PGA_RBB_2 0x011A 13 9 C_CTL_PGA_RBB_2 0x011A 7 0 PD_PGA_RBB_2 0x0115 1 OSW_PGA_RBB_2 0x0119 15 RCC_CTL_PGA_RBB_2 0x011A 13 9 C_CTL_PGA_RBB_2 0x011A 7 0 EN_LB_LPFL_RB...

Page 84: ...D_PDET_TRF_1 0x0100 3 F_TXPAD_TRF_1 0x0101 15 13 PD_PDET_TRF_1 0x0100 3 PD_TLOBUF_TRF_1 0x0100 2 PD_TXPAD_TRF_1 0x0100 1 EN_LOOPB_TXPAD_TRF_1 0x0101 0 SEL_BAND1_TRF_1 0x0103 11 EN_NEXTTX_TRF_1 0x0100 14 SEL_BAND2_TRF_1 0x0103 10 Mixer gate bias Loss control decoder PD control level shifter LO I Q generator TX PAD TX PAD matching TX power detector TX RF loopback Mixer D D S1 4 0 S2 4 0 D1 18 0 D2 2...

Page 85: ...RF_2 0x0101 15 13 PD_PDET_TRF_2 0x0100 3 PD_TLOBUF_TRF_2 0x0100 2 PD_TXPAD_TRF_2 0x0100 1 EN_LOOPB_TXPAD_TRF_2 0x0101 0 SEL_BAND1_TRF_2 0x0103 11 EN_NEXTTX_TRF_2 0x0100 14 SEL_BAND2_TRF_2 0x0103 10 Mixer gate bias Loss control decoder PD control level shifter LO I Q generator TX PAD TX PAD matching TX power detector TX RF loopback Mixer D D S1 4 0 S2 4 0 D1 18 0 D2 29 0 LO chain buffer LO mixer bu...

Page 86: ...PD_LPFIAMP_TBB_1 0x0105 3 PD_LPFLAD_TBB_1 0x0105 2 PD_LPFS5_TBB_1 0x0105 1 CG_IAMP_TBB_1 0x0108 15 10 PD_LPFH_TBB_1 0x0105 4 PD_LPFLAD_TBB_1 0x0105 2 PD_LPFS5_TBB_1 0x0105 1 EN_G_TBB_1 0x0105 0 RCAL_LPFH_TBB_1 0x0109 15 8 CCAL_LPFLAD_TBB_1 0x010A 12 8 STARTPULSE_TBB_1 0x0105 15 PD_LPFLAD_TBB_1 0x0105 2 EN_G_TBB_1 0x0105 0 RCAL_LPFLAD_TBB_1 0x0109 7 0 CCAL_LPFLAD_TBB_1 0x010A 12 8 PD_LPFS5_TBB_1 0x...

Page 87: ...B_2 0x0105 3 PD_LPFLAD_TBB_2 0x0105 2 PD_LPFS5_TBB_2 0x0105 1 CG_IAMP_TBB_2 0x0108 15 10 PD_LPFH_TBB_2 0x0105 4 PD_LPFLAD_TBB_2 0x0105 2 PD_LPFS5_TBB_2 0x0105 1 EN_G_TBB_2 0x0105 0 RCAL_LPFH_TBB_2 0x0109 15 8 CCAL_LPFLAD_TBB_2 0x010A 12 8 STARTPULSE_TBB_2 0x0105 15 PD_LPFLAD_TBB_2 0x0105 2 EN_G_TBB_2 0x0105 0 RCAL_LPFLAD_TBB_2 0x0109 7 0 CCAL_LPFLAD_TBB_2 0x010A 12 8 PD_LPFS5_TBB_2 0x0105 1 EN_G_T...

Page 88: ...GEN To CLKRX_OUT_A CLK delay To DRXI_AFE1 11 0 TX TSP To DRXQ_AFE1 11 0 TX TSP Top bias block AFE mux DAC core From DTXQ_AFE2 11 0 TX TSP From DTXI_AFE2 11 0 TX TSP From CLKDAC CLKGEN To CLKTX_OUT_B CLK delay To tbbii p n _2 TX BB To tbbiq p n _2 TX BB ADC core From rbboi p n _2 RX BB external in From rbboq p n _2 RX BB external in From pdeto p n _2 TX RF From out_rssi_rfe_2 and vrefout_rssi_rfe_2...

Page 89: ...ALIB_BIAS 0x0084 10 6 PD_PT_BIAS 0x0084 1 To vr_rext PAD To ip20frp 47 1 various blocks To ip20pt 50 1 various blocks To ip20ptrp 37 1 various blocks 10k vr_cal_ref vptat_600m BIAS mux From vr_rext PAD and vr_cal_ref internal From vptat_600m internal and vr_cal_ref internal To bias_top_adcin 1 0 AFE MUX To ADC and DAC AFE Analog signal lines Signal input output RESET_N XXXX IO control name registe...

Page 90: ...CO_SXT 1 0 0x0121 2 1 SPDUP_VCO_SXT 0x011C 14 BYPLDO_VCO_SXT 0x011C 13 CURLIM_VCO_SXT 0x011C 11 RSEL_LDO_VCO_SXT 4 0 0x0121 15 11 VDIV_VCO_SXT 7 0 0x0120 15 8 ICT_VCO_SXT 7 0 0x0120 7 0 CSW_VCO_SXT 7 0 0x0121 10 3 PD_FBDIV_SXT 0x011C 7 COARSE_START_SXT 0x0121 0 EN_DIV2_DIVPROG_SXT 0x011C 10 DIV_LOCH_SXT 2 0 0x011F 8 6 PW_DIV2_LOCH_SXT 2 0 0x011F 14 12 PW_DIV4_LOCH_SXT 2 0 0x011F 11 9 PD_VCO_COMP_S...

Page 91: ...x011C 1 SEL_VCO_SXR 1 0 0x0121 2 1 SPDUP_VCO_SXR 0x011C 14 BYPLDO_VCO_SXR 0x011C 13 CURLIM_VCO_SXR 0x011C 11 RSEL_LDO_VCO_SXR 4 0 0x0121 15 11 VDIV_VCO_SXR 7 0 0x0120 15 8 ICT_VCO_SXR 7 0 0x0120 7 0 CSW_VCO_SXR 7 0 0x0121 10 3 PD_FBDIV_SXR 0x011C 7 COARSE_START_SXR 0x0121 0 EN_DIV2_DIVPROG_SXR 0x011C 10 DIV_LOCH_SXR 2 0 0x011F 8 6 PW_DIV2_LOCH_SXR 2 0 0x011F 14 12 PW_DIV4_LOCH_SXR 2 0 0x011F 11 9 ...

Page 92: ...CGEN 19 0 0x0087 15 0 0x0088 3 0 INT_SDM_CGEN 9 0 0x0088 13 4 REV_SDMCLK_CGEN 0x0089 15 SEL_SDMCLK_CGEN 0x0089 14 EN_SDM_CLK_CGEN 0x0086 8 PD_SDM_CGEN 0x0086 3 PD_VCO _CGEN 0x0086 1 SPDUP_VCO_CGEN 0x0086 15 ICT_VCO_CGEN 7 0 0x008B 13 9 CSW_VCO_CGEN 7 0 0x008B 8 1 PD_FDIV_FBCGEN 0x0086 5 COARSE_START_CGEN 0x008B 0 DIV_OUTCH_CGEN 7 0 0x0089 10 3 PD_VCO_COMP_CGEN 0x0086 1 TST_CGEN 2 0 0x0089 2 0 Bias...

Page 93: ... Fron XCLK_TX_OUT2 XBUF TX To XCLK_RX SX RX CLKGEN and MCU BYP_XBUF_TX 0x0085 5 PD_XBUF_TX 0x0085 1 EN_OUT2_XBUF_TX 0x0085 4 PD_XBUF_TX 0x0085 1 SLFB_XBUF_TX 0x0085 7 BYP_XBUF_RX 0x0085 6 EN_TBUFIN_XBUF_RX 0x0085 3 SLFB_XBUF_RX 0x0085 8 PD_XBUF_RX 0x0085 2 BYP_XBUF_RX 0x0085 6 PD_XBUF_RX 0x0085 2 Analog signal lines Signal input output RESET_N XXXX IO control name register adress LMS7002M XBUF RX ...

Page 94: ...P_LDO_TXBUF 0x0097 3 RDIV_TXBUF 7 0 0x009A 15 8 EN_LDO_RXBUF 0x0092 4 EN_LOADIMP_LDO_RXBUF 0x0094 3 BYP_LDO_RXBUF 0x0096 0 SPDUP_LDO_RXBUF 0x0097 9 RDIV_RXBUF 7 0 0x009D 15 8 EN_LDO_DIVSXR 0x0092 10 EN_LOADIMP_LDO_DIVSXR 0x0094 9 BYP_LDO_DIVSXR 0x0096 6 SPDUP_LDO_DIVSXR 0x0097 15 RDIV_DIVSXR 7 0 0x00A0 15 8 EN_LDO_CPSXR 0x0093 7 EN_LOADIMP_LDO_CPSXR 0x0095 0 BYP_LDO_CPSXR 0x0096 13 SPDUP_LDO_CPSXR...

Page 95: ...DS_TXALML 0x00AF 5 4 CDSN_TXALML 0x00AD 4 CDS_TXBTSP 0x00AF 15 14 CDSN_TXBTSP 0x00AD 9 CDS_TXATSP 0x00AF 13 12 CDSN_TXATSP 0x00AD 8 CDS_TXBLML 0x00AF 7 6 CDSN_TXBLML 0x00AD 5 CDS_RXALML 0x00AF 1 0 CDSN_RXALML 0x00AD 2 CDS_RXBLML 0x00AF 3 2 CDSN_RXBLML 0x00AD 3 CDS_RXATSP 0x00AF 9 8 CDSN_RXATSP 0x00AD 6 CDS_RXBTSP 0x00AF 11 10 CDSN_RXBTSP 0x00AD 7 CDS_MCLK1 0x00AF 13 12 CDSN_MCLK1 0x00AD 0 CDS_MCLK...

Page 96: ..._BYP 0x0208 2 DCORRQ 0x0204 7 0 DC_BYP 0x0208 3 DCORRI 0x0204 15 8 GFIR3_BYP 0x0208 6 GFIR3_L 0x0207 10 8 GFIR3_N 0x0207 7 0 Memory space 0x0300 0x03BF GFIR1_BYP 0x0208 4 GFIR1_L 0x0205 10 8 GFIR1_N 0x0205 7 0 Memory space 0x0280 0x02BF GFIR2_BYP 0x0208 5 GFIR2_L 0x0206 10 8 GFIR2_N 0x0206 7 0 Memory space 0x02C0 0x02FF CMIX_GAIN 0x0208 15 14 CMIX_BYP 0x0208 8 CMIX_SC 0x0208 13 ISINC_BYP 0x0208 7 ...

Page 97: ...x0480 0x04BF GFIR2_BYP 0x040C 4 GFIR2_L 0x0406 10 8 GFIR2_N 0x0406 7 0 Memory space 0x04C0 0x04FF GFIR3_BYP 0x040C 5 GFIR3_L 0x0407 10 8 GFIR3_N 0x0407 7 0 Memory space 0x0500 0x05BF AGC_BYP 0x040C 6 AGC_K 0x0409 1 0 0x0408 15 0 AGC_ADESIRED 0x0409 13 2 AGC_MODE 0x040A 13 12 AGC_AVG 0x040A 11 0 RSSI 0x040B 15 0 CMIX_GAIN 0x040C 15 14 CMIX_BYP 0x040C 7 CMIX_SC 0x040C 13 MUX BIST TSG See BIST Contro...

Page 98: ...ST Counter BSTART 0x00A8 0 BSTATE 0x00A8 8 Test Vector Generator MUX MUX MUX Control Signals BENC 0x00A8 3 BENR 0x00A8 2 BENT 0x00A8 1 FRAC_SDM_CGEN 0x0088 3 0 0x0087 15 0 INT_SDM_CGEN 0x0088 13 4 EN_SDM_TSTO_CGEN 0x0086 7 EN_SDM_TSTO_SXT 0x011C 7 MIMO B EN_SDM_TSTO_SXR 0x011C 7 MIMO A FRAC_SDM_SXR 0x011E 3 0 0x011D 15 0 INT_SDM_SXR 0x011E 13 4 FRAC_SDM_SXT 0x011E 3 0 0x011D 15 0 INT_SDM_SXT 0x011...

Page 99: ...X MUX Control Signals TxTSP TXI TXQ TYI TYQ TYI TYQ TXI TXQ Figure 25 TxTSP A B BIST control structure A2 17 RxTSP A B BIST Control Diagram Signature Generator Channel Q Signature Generator Channel I BSIGQ 0x020F 14 0 0x020E 15 8 BSIGI 0x020E 7 0 0x020D 15 1 BIST FSM BIST Counter BSTART 0x0400 1 BSTATE 0x020D 0 Test Vector Generator MUX MUX Control Signals RxTSP RXI RXQ RYI RYQ RYI RYQ RXI RXQ Fig...

Page 100: ...DR 0x0022 14 LML2_FIDM 0x0023 5 LML2_TXNRXIQ 0x0023 4 LML2_MODE 0x0023 3 LML2_S3S 0x0027 15 14 LML2_S2S 0x0027 13 12 LML2_S1S 0x0027 11 10 LML2_S0S 0x0027 9 8 LML2_BQP 0x0027 7 6 LML2_BIP 0x0027 5 4 LML2_AQP 0x0027 3 2 LML2_AIP 0x0027 1 0 LML2_BB2RF_PST 0x0028 12 8 LML2_BB2RF_PRE 0x0028 4 0 LML2_RF2BB_PST 0x0029 12 8 LML2_RF2BB_PRE 0x0029 4 0 LML1_TRXIQPULSE 0x0022 13 LML1_SISODDR 0x0022 12 LML1_F...

Page 101: ...MPCFG_RXAQ 0x05C2 13 DCCAL_CMPCFG_RXAI 0x05C2 12 DCCAL_CMPCFG_TXBQ 0x05C2 11 DCCAL_CMPCFG_TXBI 0x05C2 10 DCCAL_CMPCFG_TXAQ 0x05C2 9 DCCAL_CMPCFG_TXAI 0x05C2 8 DCWR_TXAI 0x05C3 15 DCRD_TXAI 0x05C3 14 DC_TXAI 10 0 0x05C3 10 0 DCWR_TXAQ 0x05C4 15 DCRD_TXAQ 0x05C4 14 DC_TXAQ 10 0 0x05C4 10 0 DCWR_TXBI 0x05C5 15 DCRD_TXBI 0x05C5 14 DC_TXBI 10 0 0x05C5 10 0 DCWR_TXBQ 0x05C6 15 DCRD_TXBQ 0x05C6 14 DC_TXB...

Page 102: ...EASR_CMPCFG_PDET2 0x0602 1 MEASR_CMPCFG_PDET1 0x0602 0 MEASR_DAC_VAL 7 0 0x0603 7 0 MEASR_PDET2_VAL 7 0 0x0604 15 8 MEASR_PDET1_VAL 7 0 0x0604 7 0 MEASR_RSSI1_VAL 7 0 0x0605 7 0 MEASR_RSSI2_VAL 7 0 0x0605 15 8 MEASR_TPTAT_VAL 7 0 0x0606 7 0 MEASR_TREF_VAL 7 0 0x0606 15 8 MEASR_HYSCMP 2 0 0x0602 8 6 MEASR_HYSCMP 2 0 0x0602 8 6 MEASR_HYSCMP 2 0 0x0602 8 6 MEASR_HYSCMP 2 0 0x0602 8 6 MEASR_HYSCMP 2 0...

Page 103: ... for the synthesizer 2 Decision monitors the two digital outputs from the synthesizer COARSE_STEPDONE and COARSE_COMPO and makes a decision on the correct value of every bit of SWC_VCO 7 0 Input control bit of COARSE_START will be used to start each cycle 3 Normal mode setting controls are set back to the values needed for normal synthesizer operation Below are two similar algorithms one for the S...

Page 104: ...0 0x011E 13 4 Nround 4 CSW_VCO_ SXT SXR 7 0 0x0121 10 3 0 i 7 TRY_CNT 0 CSW_VCO_ SXT SXR i 0x0121 3 i 1 COARSE_START_ SXT SXR 0x0121 0 1 COARSE_STEPDONE_ SXT SXR 0x0123 15 1 TRY_CNT TRY_CNT 1 TRY_CNT MAX_TRY_CNT COARSEPLL_COMPO_ SXT SXR 0x0123 14 1 CSW_VCO_ SXT SXR i 0x0121 3 i 0 COARSE_START_ SXT SXR 0x0121 0 0 EN_COARSEPLL_ SXT SXR 0x011C 12 0 EN_INTONLY_SDM_ SXT SXR 0x011C 9 0 SPDUP_VCO_ SXT SX...

Page 105: ...gure 31 CGEN VCO Coarse tuning algorithm C code for SXT SXR VCO coarse tuning unsigned char VCO_CoarseTuning_SXT_SXR float Fref_MHz float Fvco_des_MHz unsigned char ch unsigned short Nround unsigned char i try_cnt MIMO_Ctrl ch SXT SXR selection Initialization Modify_SPI_Reg_bits 0x011C 12 12 1 1 EN_COARSEPLL 1 a VCO control voltage is switched to a DC VDD 2 Modify_SPI_Reg_bits 0x0121 0 0 0 2 COARS...

Page 106: ...rt the noise filter resistor to speed up the settling time Nround unsigned short 4 Fvco_des_MHz Fref_MHz 0 5 5 Nround round 4 Fvco_des Fref Modify_SPI_Reg_bits 0x0087 15 0 0 6 FRAC_SDM_CGEN 0 Modify_SPI_Reg_bits 0x0088 3 0 0 Modify_SPI_Reg_bits 0x0088 13 4 Nround 4 7 INT_SDM_CGEN Nround 4 Modify_SPI_Reg_bits 0x008B 8 1 0 9 Set CSW_VCO_CGEN 7 0 00000000 i 7 10 i 7 Loop Section while 1 Modify_SPI_Re...

Page 107: ...B 15 0 RP_CALIBB_BIAS 0 BestValue ADCOUT ADCOUT BestValue BestValue ADCOUT RP_CALIB_BIAS_cal RP_CALIB_BIAS RP_CALIB_BIAS RP_CALIB_BIAS 1 NO END RP_CALIB_BIAS 0x0084 10 6 RP_CALIB_BIAS_cal ratio 16 RP_CALIB_BIAS_cal NO YES YES NO YES Initialization Figure 32 Resistor calibration algorithm The following is the C code that implements described algorithm void Resistor_calibration float ratio unsigned ...

Page 108: ...g loopback path 7 the control value of the CBANK Low Band Section at the 3MHz 2 bandwidth Register the CBANK control value for the low band section for 3MHz rxMode 6 Calibrate by measurement using loopback path 7 the control value of the CBANK Low Band Section at the 5MHz 2 bandwidth Register the CBANK control value for the low band section for 5MHz rxMode 7 Calibrate by measurement using loopback...

Page 109: ...thm unsigned char Calibration_LowBand_RBB unsigned char ch unsigned char result 0 Save_config_RBB save current configuration MIMO_Ctrl ch Modify_SPI_Reg_bits 0x040A 13 12 1 AGC Mode 1 RSSI mode Algorithm_A_RBB Aproximate resistor value for RBB RBANKS Algorithm A Set_cal_path_RBB 7 Set control signals to path 7 RX LowBand if Algorithm_B_RBB LowFreqAmp 1 goto RESTORE Calibrate and Record the low fre...

Page 110: ...section for 66MHz rxMode 5 Calibrate by measurement using loopback path 8 the control value of the CBANK High Band Section at the 108MHz 2 bandwidth Register the CBANK control value for the high band section for 108MHz rxMode 6 Restore configuration Calibration_HighBand_RBB Input Parameters channel Return Parameters status Perform Algorithm_B_RBB Procedure and get Result Result TRUE YES Perform Al...

Page 111: ...rateByCap the output cuttoff frequency at 54 MHz MHz and store RESTORE Restore_config_RBB restore configuration return result A3 4 Nested algorithms A3 4 1 Algorithm A Multiply the ratio of the on chip resistor to the off chip resistor by the default control value R_CTL_LPF_RBB of the respective resistor Algorithm_A_RBB Input Parameters none Return Parameters none R_CTL_LPF_RBB 16 ratio R_CTL_LPF_...

Page 112: ...e in LowFreqAmp for later on comparison Algorithm_B_RBB Input Parameters LowFreqAmp Return Parameters status Set NCO Frequenct at 100 kHz CG_IAMP_TBB 24 CG_IAMP_TBB_ 1 2 5 0 0x0108 15 10 CG_IAMP_TBB ADCOUT RSSI 15 0 0x040B 15 0 ADCOUT 80 gain_inc 1 gain_inc 1 CG_IAMP_TBB CG_IAMP_TBB 1 CG_IAMP_TBB CG_IAMP_TBB 1 CG_IAMP_TBB_ 1 2 5 0 0x0108 15 10 CG_IAMP_TBB ADCOUT RSSI 15 0 0x040B 15 0 gain_inc 1 AD...

Page 113: ...nc CG_IAMP_TBB else CG_IAMP_TBB Modify_SPI_Reg_bits 0x0108 15 10 CG_IAMP_TBB write val to reg ADCOUT Get_SPI_Reg_bits 0x040B 15 0 RSSI value Measure the output level at the ADC input if gain_inc if ADCOUT 52428 break else if ADCOUT 52428 break if CG_IAMP_TBB 0 CG_IAMP_TBB 63 gain limit reached return 0 break LowFreqAmp ADCOUT return 1 A3 4 3 Algorithm F Algorithm steps 1 If CalFreq 10MHz then CONT...

Page 114: ..._CTL_LPFL_RBB_ 1 2 10 0 0x0117 10 0 CONTROL C_CTL_LPFH_RBB_ 1 2 7 0 0x0116 7 0 CONTROL ADCOUT RSSI 15 0 0x040B 15 0 ADCOUT LowFreqAmp CONTROL CONTROL 1 Result FALSE CONTROL 0 NO YES YES NO NO NO Return Result END Store CONTROL value Band Freq Result TRUE YES YES Figure 37 RBB algorithm F C code for algorithm F unsigned char Algorithm_F_RBB unsigned char Band_id unsigned short ADCOUT CONTROL unsign...

Page 115: ..._SPI_Reg_bits 0x0116 7 0 CONTROL write to C_CTL_LPFH_RBB RBB_CBANK MIMO_ch Band_id CONTROL Store CBANK Values RBB_STATUS MIMO_ch Band_id 1 return 1 A3 5 TBB calibration TBB calibration is divided into two calibrations for low and high bands Each calibration consist of several smaller algorithms A3 6 TBB Low Band Calibration Calibration steps 1 Save current configuration 2 Start with calibrated val...

Page 116: ...loopback path 4 the mismatch between the pre emphasis and the real pole stage Register the low pre emphasis parameters 5 5MHz 10 Calibrate by measurement using loopback path 5 the control value of the RBANK ladder only for the 2 74MHz bandwidth setting Register the value of the RBANK controls 11 Calibrate by measurement using loopback path 5 the control value of the RBANK ladder only for the 2 4MH...

Page 117: ...nd get Result Perform Algorithm_D_RBB Procedure for path 4 and get Result Perform Algorithm_E_RBB Procedure for 8 2 MHz band path 5 and get Result Perform Algorithm_E_RBB Procedure for 5 5 MHz band path 3 and get Result Reduce Real Pole RBANK value 50 Reduce PreEmphasis Zerp by 50 Perform Algorithm_D_RBB Procedure for path 4 and get Result Perform Algorithm_E_RBB Procedure for 2 7 MHz band path 5 ...

Page 118: ...band and get Result Perform Algorithm_F_RBB Procedure for 66 0 MHz band and get Result Perform Algorithm_F_RBB Procedure for 108 0 MHz band and get Result Result TRUE Restore configuration Return Result END Save current configuration Select channel AGC_MODE 1 0 0x040A 13 12 Figure 39 TBB High Band calibration algorithm The following C code implements described algorithm unsigned char Calibration_H...

Page 119: ...MHz Multiply by ratio Modify_SPI_Reg_bits 0x0109 7 0 RCAL_LPFLAD_TBB Algorithm_A_TBB Input Parameters none Return Parameters none RCAL_LPFLAD_TBB 193 ratio RCAL_LPFLAD_TBB_ 1 2 7 0 0x0109 7 0 RCAL_LPFLAD_TBB Perform Resistor_ calibration procedure and get ratio END Store 11 MHz RBANK value Figure 40 TBB algorithm A A3 8 2 Algorithm B Same as algorithm B in RBB A3 8 3 Algorithm C Algorithm steps 1 ...

Page 120: ... at the ADC input This value should be lower than LowFreqAmp if ADCOUT LowFreqAmp break If amplitude is lower than LowFreqAmp repeat cycle if CONTROL 0 return 0 CONTROL Decrease the control value CCAL_LPFLAD_TBB by one step Modify_SPI_Reg_bits 0x010A 12 8 CONTROL TBB_CBANK MIMO_ch CONTROL Store the value of CCAL_LPFLAD_TBB as the calibrated CBANK value of TBB Algorithm_C_TBB Input Parameters Band ...

Page 121: ...eq Band_id 1 Apply a single tone at frequency equal to CalFreq ADCOUT Get_SPI_Reg_bits 0x040B 15 0 RSSI value if ADCOUT LowFreqAmp inc 0 If greater then the pre emphasis zero is faster than the real pole else inc 1 while 1 ADCOUT Get_SPI_Reg_bits 0x040B 15 0 RSSI value Measure the output level at the ADC input if inc if ADCOUT 52428 break else if ADCOUT 52428 break if Zero_Freq 0 Zero_Freq 255 gai...

Page 122: ...and 1 RCAL_LPFLAD_TBB_ 1 2 7 0 0x0109 7 0 CONTROL RCAL_LPFH_TBB_ 1 2 7 0 0x0109 15 8 CONTROL ADCOUT RSSI 15 0 0x040B 15 0 ADCOUT LowFreqAmp CONTROL CONTROL 1 Result FALSE CONTROL 0 YES NO NO NO Return Result END Store CONTROL value RBANK Band Freq Result TRUE YES YES NO YES Figure 42 TBB algorithm E C code for algorithm E unsigned char Algorithm_E_TBB unsigned char Band_id unsigned short ADCOUT un...

Page 123: ...rithm B Set_NCO_Freq TBB_CalFreq Band_id Apply a single tone frequency at CalFreq while 1 ADCOUT Get_SPI_Reg_bits 0x040B 15 0 RSSI value Measure the value of the amplitude at the ADC input This value should be lower than LowFreqAmp if ADCOUT LowFreqAmp break If it is lower than LowFreqAmp repeat cycle if CONTROL 0xFF break CONTROL Increase the CONTROL value by one if low_band Modify_SPI_Reg_bits 0...

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