Lime Microsystems EVB7 Quick Start Manual Download Page 52

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LMS7002M Quick Starter Manual for EVB7 kit

52 |

P a g e

Version: 2.2

Last modified: 29/09/2014

AFE

7.9

The AFE page controls the TX and RX analog front-end interface to the digital section.

Figure 33 GUI AFE tab

A picture of the tab is shown in

Figure

. A description of each function available in this tab is

shown below in Table 12.

Table 12 GUI AFE control description

Parameter

Description

AFE

Peak current of DAC

Controls the peak current of the DAC output current. By default DAC peak current set to
325uA.

MUX input of ADC
ch 1.

Controls the MUX at the input of the ADC channel 1. By default MUX set to PGA output.

MUX input of ADC
ch 2.

Controls the MUX at the input of the ADC channel 2. By default MUX set to PGA output.

Time interleave two
analogue

signals

into one ADC

Default register set to Two ADC’s

Power down controls

AFE current mirror
in BIASTOP

Enabled AFE current mirror in BIAS_TOP when deselected. Default current mirror is
enabled.

ADC ch. 1

Enable control of ADC of channel 1. Enabled when not selected. Enabled by default.

ADC ch. 2

Enable control of ADC of channel 2. Enabled when not selected. Enabled by default.

DAC ch. 1

Enable control of DAC of channel 1. Enabled when not selected. Enabled by default.

DAC ch. 2

Enable control of DAC of channel 2. Enabled when not selected. Enabled by default.

Enable AFE module

Enabled AFE blocks when selected. By default AFE is enabled.

Summary of Contents for EVB7

Page 1: ...d Kingdom Tel 44 0 1483 685 063 Fax 44 0 1428 656 662 e mail enquiries limemicro com LMS7002M Quick Start Manual The information contained in this document is subject to change without prior notice Lime Microsystems assumes no responsibility for its use nor for infringement of patents or other rights of third parties Lime Microsystems standard terms and conditions apply at all times ...

Page 2: ...owing table shows the revision history of this document Date Version Description of Revisions 05 06 2014 2 0 Initial version 2 07 2014 2 1 Updated GUI pictures and new control descriptions 8 08 2014 2 2 Updated GUI pictures and new control descriptions and 7 23 section added 25 08 2014 2 2 Released for distribution ...

Page 3: ...b setup 19 5 2 2 TRF tab setup 20 5 2 3 TBB tab setup 20 Testing the TX Output 21 5 3 5 3 1 TX Basic Operation Checks 22 Receiver Setup and Basic Testing 23 5 4 5 4 1 SXT SXR tab setup 23 5 4 2 RFE tab setup 24 5 4 3 RBB tab setup 25 Testing the RX Output 27 5 5 5 5 1 RX Basic Operation Checks 27 Testing With Minimal Equipment 28 5 6 6 EVB7 Connectors and Options 29 Introduction to the EVB7 Connec...

Page 4: ...el Controls 42 Board Setup Si5351C and ADF4002 43 7 4 RFE 44 7 5 RBB 46 7 6 TRF 47 7 7 TBB 50 7 8 AFE 52 7 9 BIAS 53 7 10 LDO 54 7 11 XBUF 55 7 12 CLKGEN 56 7 13 SXT SXR 59 7 14 Application Note on Tuning PLLs on LMS7002M 61 7 15 LimeLight PAD 62 7 16 TxTSP 66 7 17 RxTSP 68 7 18 CDS 70 7 19 BIST 71 7 20 SPI 72 7 21 Buffers EVB7v2 74 7 22 8 Appendix A Test Equipment Setup 75 Introduction 75 8 1 Rec...

Page 5: ...ure 25 Figure 18 SXR register setup procedure 26 Figure 19 RX analog output on Spectrum Analyser 27 Figure 20 Design kit connection descriptions Top view 29 Figure 21 Design connection descriptions Bottom view 30 Figure 22 GUI window diagram 39 Figure 23 GUI Control Panel window 39 Figure 24 GUI Configuration Board Setup window 39 Figure 25 GUI Log panel 40 Figure 26 GUI Message Log tab 40 Figure ...

Page 6: ...Last modified 29 09 2014 Figure 47 GUI SPI tab 72 Figure 48 GUI Buffers EVBv2 tab 74 Figure 49 Agilent N5181A 82A MXG Front Panel 76 Figure 50 CMD window showing successful ping 79 Figure 51 CMD window with ftp connection 79 Figure 52 CMD window ftp file transfer 80 ...

Page 7: ...the easy to use GUI software The EVB7 provides system designers with the ability to connect the board to any type of baseband FPGA or CPU and allow them to implement their ideas for various wireless communication applications This document describes how to make a quick start with the LMS7002M using the EVB7 module Section 2 begins by listing the contents of the Quick Start kit Section 3 gives a ge...

Page 8: ...ontent Complete development kit content consists of Hardware o 1 EVB7 board o 1 Power supply cable that connects the EVB7 board to any lab power supply unit o 1 USB A to Micro USB B cable Software o LMS7002M GUI Control_LMS7002M o Windows drivers Documentation o Quick Starter Manual o LMS7002M datasheet o Complete PCB database o Generator waveforms ...

Page 9: ...am of the board is shown in Figure 2 The connections are shown in blue the LMS7002M chip is shown in green and the other parts are shown in orange The core of the board is the LMS7002M transceiver chip which has multiple RF analogue and digital interfaces The evaluation board includes RF matching networks for the LMS7002M These matching networks include wideband transformers to allow operation ove...

Page 10: ...d to control the LMS7002M SPI via the LMS7002M control software The USB port is converted to SPI by an on board microcontroller The HSMC connector or the 44 pin header can be used for the buffered digital interface and can be connected to compatible platforms such as the Lime Stream board The Lime Stream board also provides connections to general purpose lab equipment such as pattern generators an...

Page 11: ...lled on the board prior to shipping Section 4 1 describes the how to download the software from the Lime Microsystems web page Sections 4 2 4 3 and 4 4 describe the set up for the Windows Operating System Section 4 2 describes the installing of the USB to LMS7002M driver Section 4 3 describes the Windows OS set up Section 4 4 describes how to identify which USB port is being used Section 4 5 descr...

Page 12: ...7002M software are as follows please note that these steps may vary based on the specific version of Windows software being used and you may need to be logged in as Administrator to accomplish them 1 Connect EVB7 board to your PC via the USB cable 2 Go to Control Panel System Device Manager 3 Locate USB to LMS7002M under Other devices and press right click to select Properties Figure 3 Figure 3 De...

Page 13: ...ed 29 09 2014 Figure 4 Device properties 5 Select Browse my computer for driver software locate the driver provided with EVB7 board and press Next Figure 5 Figure 5 Update Driver Wizard 6 If the Windows Security window appears select Install this driver software anyway Figure 6 ...

Page 14: ...e 6 Hardware wizard Install driver manually Windows should proceed to install drivers at this stage Generally once the above steps have been taken for the EVB7 these steps do not need to be repeated IMPORTANT Before running the control software unplug then plug your device back into your computer ...

Page 15: ...stallation Windows will assign to your EVB7 board a serial port To check your board serial port number please follow these steps 1 Go to Control Panel System Device Manager 2 Locate USB Virtual Serial Port under Ports COM LPT Note that in this system example it has enumerated as COM2 Figure 7 Figure 7 Check for new communication port ...

Page 16: ...nder administrator privileges To do that right click on the Control LMS7002M icon and select Run as an Administrator This will provide administrator privileges which are required for EVB7 board communication via USB Connecting 4 7 Once the Windows driver is installed and the control software has been lunched click on Options Connection Settings The Connection Setting windows will pop up Figure 8 F...

Page 17: ...LMS7002M Quick Starter Manual for EVB7 kit 17 P a g e Version 2 2 Last modified 29 09 2014 Figure 9 GUI detected device and firmware version ...

Page 18: ...rd Section 5 2 describes the set up of the transmitter with Section 5 2 1 describing how to set up the SXT TX PLL and Section 5 2 2 describing how to set up the TX analogue baseband and RF tabs of the LMS7002M Control software Section 5 4 describes the set up of the transceiver for basic tests with section 5 4 1 describing how to set up the SXR RX PLL and Section 5 4 2 and 5 4 3 describing how to ...

Page 19: ...wn in Figure 10 To generator settings are described in Section 8 3 Appendix A Figure 10 Tx Test Setup 5 2 1 SXT SXR tab setup After power up connect the GUI to the board and select the SXT SXR tab To configure the Tx LO to 2140 MHz do the following 1 Select the B SXT in the configuration channels window to control TxPLL 2 Enable Tx PLL VCO Deselect 3 Set Scales VCO bias current to 255 4 Type the w...

Page 20: ...as the output path For this test we are not going to change these settings 5 2 3 TBB tab setup In the TBB tab the baseband gain and filter bandwidth are controlled Follow the instructions below set up TBB 1 Select the A SXR to control channel A 2 Set Frontend gain and reference bias current of IAMP 3 Configure the base band filter settings 4 Select the analog input path to current amplifier See Fi...

Page 21: ...in section 5 2 the TX1_A output socket X1 can be connected to a spectrum analyzer SA The SA you can now observe the results of this basic operational test Figure 13 The test is looking at the DC offset from the un programmed data DAC as LO leakage and the example shown below is measuring a value of 26 8dBm Figure 13 Basic TX testing using DC offset resulting in LO leakage Step 1 Step 2 Step 3 Step...

Page 22: ...n Checks To check the basic TX frequency and gain control conduct some tests changing frequencies and gain settings The following four tests are recommended TRF TXPAD gain change setting from 0 to 31 and observe results LO should vary by approx 1 dB steps 31dB range Change frequency from 2 14 GHz to 2 11 GHz and press Calculate Tune CAP value should change check the Spectrum Analyzer Change freque...

Page 23: ...ing the Analog output from connector X40 Figure 15 Rx Test Setup 5 4 1 SXT SXR tab setup Select the SXT SXR tab To configure the Rx LO to 1950 MHz do the following 6 Select the A SXR in the configuration channels window to control RxPLL 7 Enable Rx PLL VCO Deselect 8 Set Scales VCO bias current to 255 9 Type the wanted frequency in Frequency GHz box In this case 1950 MHz 10 Press Calculate followe...

Page 24: ...e receiver RF front end Follow the configuration steps below 1 Enable LNARFE RXFE TIA and RFFE Quadrature LO generator 2 Select active LNA Select LNAW for this test 3 Configure TIA reference current settings 4 Configure LNA core current settings 5 Configure Input switches Deselect input of LNAW and select LNAL See Figure 17 below to check selections Step 1 Step 2 Step 4 Step 3 Step 5 ...

Page 25: ... RBB tab setup Select the TBB tab to configure the PGA gain and baseband filter bandwidths Follow the configuration steps below 1 Set PGA gain to 19 dB 2 Configure filter bandwidth 3 Select PGA output to output pads This selection enables receiver analog outputs See Figure 18 below to check selections Step 1 Step 2 Step 4 Step 3 Step 5 ...

Page 26: ...LMS7002M Quick Starter Manual for EVB7 kit 26 P a g e Version 2 2 Last modified 29 09 2014 Figure 18 SXR register setup procedure Step 1 Step 3 Step 2 ...

Page 27: ...5 1 RX Basic Operation Checks To check the basic Rx frequency and gain control conduct some tests changing frequencies and gain settings The following six tests are recommended a RBB change PGA gain setting from 19 to 12 observe results gain should decrease b RFE change TIA gain settings from Gmax to Gmin observe results gain should decrease c RFE LNA gain change from Gmax to Gmax 30 observe resul...

Page 28: ...ble to link the TX1_A output X1 to the receiver input LNAW_A input X5 and rely on the LO leakage to provide an input signal to the RX Using the methods of Section 5 2 and Section 5 4 set the SXT to 2140 MHz and SXR to 2145 MHz and measure a 5 MHz signal with an oscilloscope to observe the RXI output at X19 The magnitude of the output signal can be controlled with the various gain controls in the R...

Page 29: ...rs and Options 6 1 Section 6 2 describes the various connectors available on the EVB7 Section 6 3 describes the hardware options available on the EVB7 including reference clocks and the SPI control The top and bottom of the board are shown in Figure 20 and Figure 21 respectively Board Connections 6 2 Figure 20 Design kit connection descriptions Top view ...

Page 30: ...egulator that converts 12 V to 5 V J5 USB USB Connector to PC J6 FMC The FMC HPC is a standard connector used to interface the Lime board directly to an FPGA design kit The signal pin description is shown in 6 2 1 section J7 Digital I O Connector This connector provides access to externally buffered LMS70002M digital interface and SPI interface Signal pin description showed in 6 2 2 section J8 5V ...

Page 31: ...er bands receiver input X12 LNAW_B Receiver LNA_W input channel B Wideband receiver input X18 CLK I O Reference clock input used to synchronize test equipment with EVB7 board to calibrate frequency error A 10 MHz reference from the test equipment connects to X18 connector X19 X20 X39 X40 RXBUFFI Q Receiver analog single ended outputs X16 X17 X25 X28 X37 X38 RXOUTI Q Receiver analog differential ou...

Page 32: ... Clock from BBIC to RFIC during JESD207 mode Port 2 H14 RXEN RX hard power off G12 RXMCLK Clock from RFIC to BBIC during JESD207 mode Port 2 G13 RXIQSEL IQ flag in RXTXIQ mode enable flag in JESD207 mode Port 2 D14 RESET Hardware reset active low CMOS D15 IQSEL1_DIR IQSEL direction control for port 1 If 1 input 0 output C14 SDO Serial port data out CMOS C15 DIO_DIR_CTRL2 Data direction control for...

Page 33: ...uffer enable disable If 1 disable 0 enable C31 SDA I2C port data line CMOS C30 SCL I2C port clock line CMOS D12 RSSI_ADC0 Analog test point C10 RSSI_ADC1 Analog test point 6 2 2 Digital I O connector pin description The DIO card can be connected to EVB 7 via Digitail I O connector J7 Connectr has 44 pins The pin description showed in the Table 3 Table 3 Digital I O connector pin description Pin nu...

Page 34: ... LimeLight protocol control 34 SynCLK1 Clock Out CMOS 35 RXFCLK Clock from BBIC to RFIC during JESD207 mode Port 2 36 RXIQSEL IQ flag in RXTXIQ mode enable flag in JESD207 mode Port 2 37 RXMCLK Clock from RFIC to BBIC during JESD207 mode Port 2 38 RXEN RX hard power off 39 TXNRX2 LimeLight protocol control 40 SAEN Serial port A enable active low CMOS 41 SCLK Serial port clock positive edge sensiti...

Page 35: ...board can accept three different types of TCXO s as described in Table 4 Table 4 TCXO Configurations Size Reference number Part Number Description 14 7x9 2 XO2 E5405LF 61 44 MHz Crystal oscillator used in combination with divider 2 U10 for performance improvements 7x5 4pin XO1 E5280LF 30 72 MHz crystal shipped with the board as a default 7x5 6pin XO3 E6245LF 30 72 MHz high performance crystal osci...

Page 36: ...Options SPI control Configuration DEFAULT MODE USB connector or baseband connector J7 SPI controlled via J6 baseband connector Description SPI controlled via USB or J7 connector SPI connected to BB via connector J6 HSMC Component R91 NF 0R R92 NF 0R R93 NF 0R R94 NF 0R R95 NF 0R R96 NF 0R All of these components are located on the underside of the board Note The USB interface must be left disconne...

Page 37: ..._A Broadband from 4 5 3000MHz using TC1 1 13MA Balun X3 X44 LNAL_A Broadband from 4 5 3000MHz using TC1 1 13MA Balun X4 X45 LNAH_A Broadband from 10 6000MHz using TCM1 63AX Balun X5 X46 LNAW_A Broadband from 10 6000MHz using TCM1 63AX Balun X8 X47 TX1_B Broadband from 10 6000MHz using TCM1 63AX Balun X9 X48 TX2_B Broadband from 4 5 3000MHz using TC1 1 13MA Balun X10 X49 LNAL_B Broadband from 4 5 3...

Page 38: ... GUI control panel LMS7002M register and EVB7 board configuration panel and LOG panel These are shown in Figure 22 7 2 1 GUI Control panel GUI Control panel includes menu bar and various control buttons for controlling the software These will be described in detail in Section 7 3 The GUI control panel is shown in Figure 23 7 2 2 Configuration panel Configuration panel controls the LMS7002M registe...

Page 39: ...t 39 P a g e Version 2 2 Last modified 29 09 2014 Figure 22 GUI window diagram Figure 23 GUI Control Panel window Figure 24 GUI Configuration Board Setup window LMS7002M Registers and EVB7 Board Configuration Panel LOG Panel GUI Control Panel ...

Page 40: ...e information you want to log The logged messages can be saved into txt file In the lower left corner of the log tab the evaluation board version and firmware version is displayed The Menu Bar 7 3 7 3 1 The File Menu In the File menu you can select to start new projects save current GUI project saved in ini or txt format or open previously saved project Saved project file contains complete registe...

Page 41: ...each channel as shown in Figure 27 Figure 27 GUI Register Map window 7 3 4 The Help Menu The help menu contains one option giving the software version and build date It also contains the contact details for Lime Microsystems 7 3 5 The Button Menu The button menu contains 6 buttons controls and 3 other minor controls The new open save buttons are identical to those in the File menu of Section 7 3 1...

Page 42: ...ed A SXR front panel will display Active Ch SXR or Active Ch A If selected B SXT front panel will display Active Ch SXT or Active Ch B The display shows information depending which configuration tab you are currently and which channel is selected The SXR option is used for setting the receive synthesizer parameters in the SXT SXR tab see Section 7 14 The SXT option is used for setting the transmit...

Page 43: ...ct the green PLL locked LED LD2 on the interface board should illuminate LD2 is located in the upper left hand corner of the interface board Make sure that the Fvco value corresponds to the frequency of TCXO The Si5351C is a dual PLL for frequency conversion in the 10 100MHz range It can be used to provide programmable clock signals to external hardware through the external digital interfaces and ...

Page 44: ...for RF loopback RXFE mixer buffer Power control signal for RXFE mixer lo buffer Must be deselected in normal operation RXFE Quadrature LO generator Power control signal for RXFE quadrature LO generator Must be deselected in normal operation RXFE RSSI Power control signal for RXFE RSSI Enables RSSI readings when powered on RXFE TIA Power control signal for RXFE TIA Must be deselected in normal oper...

Page 45: ...NA input Controls the Q of the input LNA matching circuit and provides tradeoff between gain NF and IIP2 3 The higher the frequency the lower value should be Also the higher value lower the Q Default value is 6 Compensation resistor of TIA opamp Controls the compensation resistors of the TIA operational amplifier Recommended value is 5 Sets feedback resistor value Sets the TIA feedback resistor va...

Page 46: ... when selected Default value is disabled PGA input Controls PGA input path There are a total five different inputs to the PGA 1 LPFL output connected to PGA 2 LPFH output connected to PGA 3 Bypass LPF blocks output connected to PGA 4 Tx baseband loopback connected to PGA 5 TXRF peak detector connected to PGA Concurrently only one path can be selected as PGA input Default path is LPFL output connec...

Page 47: ...ompensation of the LPFL operational amplifier Control range from 0 to 5 Default values set to 5 Input stage reference bias current RBB_LPF Controls the reference bias current of the input stage of the operational amplifier used in LPF blocks Low or High Must increase up to 24 when a strong close blocker is detected to maintain the linearity performance Control range from 0 to 31 Default values set...

Page 48: ...t Controls TXPAD output capacitor used for fine tuning Control range from 0 to 7 Default is set to 3 Loss of loopback path at TX side Controls Tx loopback path gain Default gain is set to 24 dB TXPAD linearizing part gain Controls TXPAD linearization gain Control range from 0 to 31 Default is set to 0 TXPAD gain and output power Controls the gain of TXPAD Control range from 0 to 31 Default is set ...

Page 49: ...e TXPAD Control range from 0 to 31 Default is set to 12 Power down controls Power detector Enables power detector when deselected By default power detector is powered down TX LO buffers Enables TX LO buffer By default TX LO is enabled TXPAD Enables TXPAD block By default TXPAD is enabled Enable TRF modules Power down all TFE blocks when deselected By default TRF blocks enabled Direct Control Enabl...

Page 50: ...range from 0 to 63 Default is set to 24 Reference bias current of IAMP main bias current source This controls the reference bias current of the IAMP main bias current sources Control range from 0 to 31 Default is set to 12 Reference bias current of IAMP cascode transistors gate voltage This controls the reference bias current of the IAMP s cascode transistors gate voltages that set the IAMP s inpu...

Page 51: ... biquad Enables LPFH filter when deselected By default filter is powered down LPFIAMP front end current amp Enables LPF current amplifier when deselected By default current amplifier is enabled LPFLADTBB low pass ladder filter Enables LPF ladder when deselected By default current amplifier is enabled LPFS5TBB low pass real pole filter Enables LPF real pole filter when deselected By default real po...

Page 52: ...ult MUX set to PGA output MUX input of ADC ch 2 Controls the MUX at the input of the ADC channel 2 By default MUX set to PGA output Time interleave two analogue signals into one ADC Default register set to Two ADC s Power down controls AFE current mirror in BIASTOP Enabled AFE current mirror in BIAS_TOP when deselected Default current mirror is enabled ADC ch 1 Enable control of ADC of channel 1 E...

Page 53: ...ting is set to enabled PTAT RP block Enable signal for PTAT RP block when not selected Default register setting is set to enabled PTAT Enable signal for PTAT block when not selected Default register setting is set to enabled Enable central bias block Enable signal for central bias block Default register setting is set to enabled Power down all block Enables BIAS block when selected By default BIAS...

Page 54: ...downs Bias Noise filter tab figure above divided in separate sections Power control Short noise filter resistor Bias In Power control section is the SPI controls are in groups related to their function These controls enable the LDO for the particular block Short noise filter resistor bypasses noise filtering resistor By default enabled Bias section enables the load dependent bias to optimize the l...

Page 55: ...ion 2 2 Last modified 29 09 2014 Figure 36 GUI LDO Voltages tab XBUF 7 12 XBUF page controls the TX and RX PLL clock pin input configurations to provide a reference frequency for SXT and SXR respectively The CLKGEN PLL uses the SXR Clock Figure 37 GUI XBUF tab ...

Page 56: ...the input 3 3V buffer in XBUF TX Shorts the Input of 3 3V buffer in XBUF By default disabled EN_OUT2_XBUF_TX Enables the 2nd output of TX XBUF By default buffer is disabled This control is intended to internally rout TX PLL CLK to SXT and SXR by an internal path EN_TBUFIN_XBUF_RX Disables the input from the external XO By default buffer is disabled This control is intended to internally rout TX PL...

Page 57: ...ode of SX Controls the test mode of the SX Available test modes 0 TST disabled By default test mode disabled 1 tstdo 0 CLKH1 tstdo 1 CLKH2 2 tstdo 0 CLK_SDM tstdo 1 DIV_CLK 2 tstao vco_vtune through a 50Kohm resistor 3 tstdo 0 REFCLK tstdo 1 DIV_CLK 3 tstao vco_vtune through a 10Kohm resistor 5 tstdo 0 PFD UP tstdo 1 PFD DN REV_CLKDAC_CGEN Inverts the clock F_CLKL for TX TSP By default is not inve...

Page 58: ... default set to 128 Scales VCO bias current Scales the VCO bias current from 0 to 2 5xInom Control range from 0 to 31 Default value 12 PLL filter CP2 Controls the value of CP2 cap from CP output to GND in the PLL loop filter Control range from 0 to 5688fF Default value 2275 2 fF CP3 Controls the value of CP3 cap from CP output to GND in the PLL loop filter Control range from 0 to 3720fF Default va...

Page 59: ...d frequency in Frequency GHz box In this case 1950MHz 5 Press Calculate followed by Tune A picture of the tab is shown in Figure 39 A description of each function available in this tab is shown below in Table 16 Table 16 GUI SXT SXR control description Parameter Description Division ration Trim duty cycle of DIV2 LOCH Trims the duty cycle of DIV2 LOCH Only works when forward divider is dividing by...

Page 60: ... the SX LDO By default LDO is bypassed Enable current limit Enables the output current limitation in the VCO regulator By default enabled Enable INTEGR_N mode Enables INTEGER N mode of the SX By default SX is set to Frac N mode Enable SDM_TSTO_SXR outputs Enables the SDM_TSTO outputs for SXR testing purposes By default is disabled Reverse SDM clock Inverts DSM clock By default clock is not inverte...

Page 61: ...s on LMS7002M 7 15 The LMS7002M has three synthesisers SXT SXR and CLKGEN The LMS7002M Control Software uses a simple tuning algorithm to control these The minimum and maximum frequencies of each VCO are defined in the VCO PARAMS control for each VCO This allows linear interpolation of CSW_VCO control when using the Tune control Further frequencies could be added to the VCO PARAMS table to allow q...

Page 62: ...resistor of SDIO pad Pull up enabled by default Engage pull up of SCLK pad Controls Pull up resistor of SCLK pad Pull up enabled by default Engage pull up of DIQ2 pad Controls Pull up resistor of DIQ2 pad Pull up enabled by default Engage pull up of TXNRX2 pad Controls Pull up resistor of TXNRX2 pad Pull up enabled by default Engage pull up of MCLK2 pad Controls Pull up resistor of MCLK2 pad Pull ...

Page 63: ... memory Rx MIMO ch A Resets configuration memory to the default state for Rx MIMO channel A logic By default RESET inactive Tx FIFO soft reset Soft reset of LimeLight TX FIFO registers By default RESET inactive Driver strength SDA pad Set SDA pad driver strength to 4mA or 8 mA By default set to 4 mA SCL pad Set SCL pad driver strength to 4mA or 8 mA By default set to 4 mA SDIO pad Set SDIO pad dri...

Page 64: ...I is selected Sample source when Port1 is Rx BQ sample position Select BQ sample position in frame Position 3 2 1 or 0 By default position set to 3 BI sample position Select BI sample position in frame Position 3 2 1 or 0 By default position set to 2 AQ sample position Select AQ sample position in frame Position 3 2 1 or 0 By default position set to 1 AI sample position Select AI sample position i...

Page 65: ...to 1 Clock cycles to wait before data drive start Controls the number of clock cycles to wait before data drive stop after burst start is detected in JESD207 mode on Port 1 and Port 1 is transmitter By default set to 1 Clock cycles to wait before data capture stop Controls the number of clock cycles to wait before data capture stop after burst stop is detected in JESD207 mode on Port 1 and Port 1 ...

Page 66: ...MIX By default set to downconvert Start BIST Starts TxTSP built in self test Keep it at 1 one at least three clock cycles Bypass CMIX Bypass CMIX module when selected GFIR3 Bypass GFIR3 module when selected GFIR1 Bypass GFIR1 module when selected Gain correction Bypass Gain correction module when selected ISINC Bypass ISINC module when selected GFIR2 Bypass GFIR2 module when selected DC Correction...

Page 67: ...efault 2047 Phase corrector Sets Phase corrector value Control range from 0 to 2047 By default 0 Interpolation HBI ratio Sets HBI interpolation ratio Possible control values 2 4 8 16 32 and bypass By default bypassed TSG Swap I and Q signal Swap IQ signals at test signal generator s output By default not selected TSGFCW Select frequency generated by test NCO By default TSG frequency set to the TSP...

Page 68: ...CMIX By default set to downconvert Start BIST Starts RxTSP built in self test Keep it at 1 one for at least three clock cycles Bypass CMIX Bypass CMIX module when selected GFIR3 Bypass GFIR3 module when selected GFIR1 Bypass GFIR1 module when selected Gain correction Bypass Gain correction module when selected AGC Bypass AGC module when selected GFIR2 Bypass GFIR2 module when selected DC Correctio...

Page 69: ...es 2 4 8 16 32 and bypass By default bypassed TSG Swap I and Q signal Swap IQ signals at test signal generator s output By default not selected TSGFCW Select frequency generated by test NCO By default TSG frequency set to the TSP clock divided by 8 TSGMODE Select test signal generator mode NCO or DC By default NCO is selected Input Source Select input source to TSP ADC input or TSG By default LML ...

Page 70: ...B channel clock inversion control By default clock is not inverted TX LMLA TX LML interface A channel clock inversion control By default clock is not inverted RX LMLB RX LML interface B channel clock inversion control By default clock is not inverted RX LMLA RX LML interface A channel clock inversion control By default clock is not inverted MCKL2 MCLK2 clock inversion control By default clock is n...

Page 71: ...delay Clock can be delayed by 200 ps 500 ps 800 ps and 1100 ps By default clock delayed 200 ps RX LML A RX LML A clock delay Clock can be delayed by 200 ps 500 ps 800 ps and 1100 ps By default clock delayed 200 ps BIST 7 20 The Build In Self Test BIST modules for SXT SXR and CGEN controls are described in this chapter Figure 45 GUI BIST tab The BIST modules are used for the test proposes only Ther...

Page 72: ...he register map description Every SPI register of the LMS7002M can be read back A picture of the tab is shown in Figure 46 A description of each function available in this tab is shown below in Table 24 Figure 46 GUI SPI tab Table 23 GUI SPI control description Parameter Description Write Address Hex Register address in HEX format Value Hex Register value in HEX format Status Previously executed c...

Page 73: ...function results to txt file to selected location Start addr hex Start register read write interval End addr hex End register read write interval TOP Lime Light LimeLight interval 0x0020 0x002e Bias BIAS interval 0x0083 0x0084 CGEN CGEN interval 0x0086 0x008d BIST BIST interval 0x00a8 0x00ad AFE AFE interval 0x0082 0x0084 XBUF XBUF interval 0x0085 0x0086 LDO LDO interval 0x0092 0x00a7 CDS CDS inte...

Page 74: ...Buffers DIO_DIR_CTRL1 On board buffers direction control for Port 1 If selected Port 1 is receiver DIO_DIR_CTRL2 On board buffers direction control for Port 2 If selected Port 2 is receiver DIO_BUFF_OE If selected set onboard buffers to Hi Impedance state IQSEL1_DIR On board buffers IQSEL pin direction control for Port 1 If selected Port 1 is receiver IQSEL2_DIR On board buffers IQSEL pin directio...

Page 75: ...ue TX inputs of the LMS7002M This procedure is not required when the LMS7002M chip is driven digitally by a baseband processor Recommended Test Equipment 8 2 The following test equipment is recommended for the testing of EVB7 It is possible to use other test equipment but the alternatives may not provide all the necessary features N5182A MXG o Differential Arbitrary Waveform Generator Option 1EL N...

Page 76: ... I Q Adjustments softkey 3 softkey 1 highlights off on ii If not press I Q Adjustments softkey 3 softkey 1 highlighted section should alternate between on and off when pressed iii press return iv Check text next to I Q softkey 3 softkey 1 highlights off on v If not press I Q softkey 3 softkey 1 highlighted section should alternate between on and off when pressed There should now be a 0 3 V common ...

Page 77: ...ling factor of 30 clock 15 36 MHz EDGE3 wfm GSM EDGE modulated test signal clock 13 MHz To download files to the signal generator follow the process described in section 9 3 3 To apply the correct file 1 Press Mode button 23 2 Press Dual Arb softkey 3 softkey 1 3 Press Select waveform softkey 3 softkey 2 4 Use up down arrows 5 or spin knob 18 to select the wanted waveform from list 5 Press Select ...

Page 78: ...f button to toggle the modulation on and off Note The Mod on off button turns the modulation on to the RF output and IQ output simultaneously The RF does not need to be on for the IQ outputs to work 8 3 3 Downloading wfm Files to the Signal Generator The following process should allow you to download files to the Agilent signal generator The same process works for MXG and ESG This can be done via ...

Page 79: ...ime Waveform In the Command Prompt window set the directory to the one where the wfm files are located using the CD command Use FTP to send files to the signal generator Type ftp 192 168 2 92 as shown in Figure 50 Figure 50 CMD window with ftp connection If you are correctly connected then the above should be returned Press return twice for user name and password none needed Type cd bbg1 Type cd w...

Page 80: ... EVB7 kit 80 P a g e Version 2 2 Last modified 29 09 2014 Figure 51 CMD window ftp file transfer To exit the ftp program type bye To close the Command Prompt window type exit The wfm files should now be visible in the list of ARB files ...

Page 81: ...r in connection with the Materials including your use of the Materials including for any direct indirect special incidental or consequential loss or damage including loss of data profits goodwill or any type of loss or damage suffered as a result of any action brought by a third party even if such damage or loss was reasonably foreseeable or Lime Microsystems had been advised of the possibility of...

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