LG T5100, Service Manual, Page: 17 / 136

2. TECHNICAL BRIEF
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2.7 Digital Baseband
A. General Description
CALYPSO is a chip implementing the digital base-band processes of a GSM/GPRS mobile phone.
This chip combines a DSP sub-chip (LEAD2 CPU) with its program and data memories, a Micro- -
Controller core with emulation facilities (ARM7TDMIE), internal 8Kb of Boot ROM memory, 4M bit
SRAM memory, a clock squarer cell, several compiled single-port or 2-ports RAM and CMOS gates.
The chip will fully support the Full-Rate, Enhanced Full-Rate and Half-Rate speech coding.
CALYPSO implements all features for the structural test of the logic (full-SCAN, BIST, PMT, JTAG
boundary-SCAN).
B. Block Description
CALYPSO architecture is based on two processor cores ARM7 and DSP using the generic RHEA bus
standard as interface with their associated application peripherals.
CALYPSO is composed from the following blocks:
ARM7TDMIE : ARM7TDMI CPU core
DSP subchip
ARM peripherals:
General purpose peripherals
ARM Memory Interface for external RAM, Flash or ROM
4 Mbit Static RAM with write-bufferns
Figure 10. Top level block diagram of the Calypso G2