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Copyright © 2014 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
6. CIRCUIT DIAGRAM
R2302
0
0
R2303
2.2u
C2304
2.2u
C2305
1u
C2326
C2300
10u
C2322
0.1u
0.1u
C2323
0.1u
C231
4
C231
9
0.1
u
0
R2300
0
R2301
0.1u
C2324
C2327
1u
C2328
0.1u
DNI
C2325
+1V8_MTK_VIO
+1V8_MTK_VIO
+1V8_MTK_VIO
+1V8_MTK_VCN
+2V8_MTK_VTCXO
+1V8_MTK_VIO
+3V3_MTK_VUSB
+1V8_MTK_VIO
+1V15_MTK_PROC
+2V8_MTK_VIO
+3V3_MTK_VMC
83
83
+1V8_MTK_VIO
+1V2_MTK_LPDDR2
C2310
0.1u
0.1u
C2311
103
103
0.1u
C232
0
0.1u
C232
1
120 121 122 123
124
C2306
1u
C2307
1u
1u
C2308
C2309
1u
C231
5
0.1
u
0.1u
C231
6
C231
7
0.1
u
0.1u
C2312
0.1u
C2313
C2301
10u
10u
C2302
C2303
4.7u
1u
C231
8
U16
U15
U14
U13
U12
J17
T17
T16
J16
J15
J14
J11
J10
J9
J8
R17
M17
M10
M9
M8
M7
M6
L17
L9
L8
L7
L6
K17
K16
K15
K14
K12
K11
K9
K8
K7
K6
U2100
MT6572M
C10
K24
W24
AB24
H13
J19
L3
K20
AA1
F18
E2
C3
A4
A1
D3
U9
E5
F1
G23
G24
H23
P25
R25
U25
T25
U7
U6
T9
T8
T7
T6
R9
R8
R7
R6
P9
P8
P7
P6
W19
W16
W14
W12
W9
U17
VCCK_1
VCCK_2
VCCK_3
VCCK_4
VCCK_5
VCCK_6
VCCK_7
VCCK_8
VCCK_9
VCCK_10
VCCK_11
VCCK_12
VCCK_13
VCCK_14
VCCK_15
VCCK_16
VCCK_17
VCCK_18
VCCK_19
VCCK_20
VCCK_21
VCCK_22
VCCK_23
VCCK_24
VCCK_25
VCCK_26
VCCK_27
VCCK_28
VCCK_29
VCCK_30
VCCK_31
VCCK_32
VCCK_33
VCCK_34
VCCK_35
VCCK_36
VCCK_37
VCCK_38
VCCIO_EMI_1
VCCIO_EMI_2
VCCIO_EMI_3
VCCIO_EMI_4
VCCIO_EMI_5
VCCK_CPU_1
VCCK_CPU_2
VCCK_CPU_3
VCCK_CPU_4
VCCK_CPU_5
VCCK_CPU_6
VCCK_CPU_7
VCCK_CPU_8
VCCK_CPU_9
VCCK_CPU_10
VCCK_CPU_11
VCCK_CPU_12
VCCK_CPU_13
VCCK_CPU_14
DVDD18_MIPIRX
DVSS18_MIPIRX
DVDD18_MIPITX
DVSS18_MIPITX
AVDD18_USB
AVDD33_USB
AVSS33_USB
AVDD28_DAC
AVDD18_AP
DVDD18_PLLGP
AVDD18_MD
AVSS18_MD_1
AVSS18_MD_2
AVSS18_MD_3
AVSS18_MD_4
AVDD18_WBG
DVDD18_MC0
DVDD18_CAM
DVDD18_VIO_1
DVDD18_VIO_2
DVDD18_VIO_3
DVDD18_LCD
DVDD3_LCD
DVDD3_MC1
DVDD28_BPI
0.1u
C2329
VPROC_FB
GND_VPROC_FB
Size is changed ( 12/26 )
Size is changed ( 12/26 )
Note 1
Note 2
(i.e : DO NOT use VIO18 when touch is RTP)
3. no use AUXADC, no RTP
AVDD18_AP = VIO18
cap = none (share with C2314)
cap = 0.1 uF (NC)
< 2- MT6572_POWER > Rev_0.1
AVDD18_AP = VIO18
2. use AUXADC, no RTP
cap = 0.1 uF
AVDD18_AP = ext. 1.8V LDO
1. use RTP (Resistive Touch Panel)
Based on your system level design
DVSS18_MIPITX(P25) --> C2320
DVSS18_MIPIRX(U25) --> C2321
Dedicate VSS ball, must return to cap then to main GND
Cap close to BB IC
differential 4mil with good shielding,
Vproc remote sense :
120mil
please refer to FM desense performance enhance proposal.
Based on your system level design, if better FM performance is needed on your system,
recommand < 150mil
for eMMC
If single-sided SMT, put around Memory.
If double-sided SMT, put below BB.
Close to BB IC,
Close to MT6572
Rev_0.3
<2-3-2-1-3_MT6572M_POWER>
4mil - differential - GND shielding
Note 3
Note 2
from the BB to PMIC