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3. TECHNICAL BRIEF
- 43 -
LGE Internal Use Only
Copyright © 011 LG Electronics. Inc. All right reserved.
Only for training and service purposes
Figure. 3.7.3 DDR SDRAM Part Block Diagram
3.7.1.2 DDR SDRAM
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Double Data Rate architecture
-two data transfer per clock cycle
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x16 bus width
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Supply Voltage
-VDD / VDDQ = 1.7 - 1.95 V
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Memory Cell Array
-8Mb x 4Bank x 16 I/O
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Bidirectional data strobe (DQS)
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Input data mask signal (DQM)
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Input Clock
-Differential Clock Inputs (CK, /CK)
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MRS, EMRS
-JEDEC Standard guaranteed
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CAS Latency
-Programmable CAS latency 2 or 3 supported
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Burst Length
- Programmable burst length 2 / 4 / 8 with both sequential
and interleave mode
[ DDR SDRAM ]