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Copyright © 2014 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
6. CIRCUIT DIAGRAM
TESTMODE
FSOURCE_P
VRT
VBIAS
AUX_XM
AUX_XP
AUX_YM
AUX_YP
AUX_IN0
AUX_IN1
REFP
USB_VRT
RCLK0
RCKE
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
RA8
RA9
RDQM0
RDQM1
RDQM2
RDQM3
RDQS0
RDQS1
RDQS2
RDQS3
RDQ0
RDQ1
RDQ2
RDQ3
RDQ4
RDQ5
RDQ6
RDQ7
RDQ8
RDQ9
RDQ10
RDQ11
RDQ12
RDQ13
RDQ14
RDQ15
RDQ16
RDQ17
RDQ18
RDQ19
RDQ20
RDQ21
RDQ22
RDQ23
RDQ24
RDQ25
RDQ26
RDQ27
RDQ28
RDQ29
RDQ30
RDQ31
REXTDN
SYSRSTB
TP_MEMPLL
VREF
RCS0_B
RCS1_B
RCLK0_B
RDQS0_B
RDQS1_B
RDQS2_B
RDQS3_B
UL_I_P
UL_I_N
UL_Q_P
UL_Q_N
DL_I_P
DL_I_N
DL_Q_P
DL_Q_N
APC
DVDD18_EFUSE
CLK26M
USB_DP
USB_DM
CHD_DP
CHD_DM
XIN_WBG
GPS_RXQN
GPS_RXQP
GPS_RXIN
GPS_RXIP
WB_TXQN
WB_TXQP
WB_TXIN
WB_TXIP
WB_RXQN
WB_RXQP
WB_RXIN
WB_RXIP
AVSS_REFN
2_3_3_1_1_MT6582_DATA_V0_3_0402203716
218
218
VREF_LPDDR3
+1V8_MTK_VIO
+1V8_MTK_VIO
BB_CLK
WLAN_CLK
USB_D_P
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
USB_D_M
PCB_REVISION
PCB_REVISION
SYS_RESIN_N
SYS_RESIN_N
CHG_D_N
CHG_D_P
EBI_CA_0
EBI_CA_1
EBI_CA_2
EBI_CA_3
EBI_CA_4
EBI_CA_5
EBI_CA_6
EBI_CA_7
EBI_CA_8
EBI_CA_9
EBI_CS_1
EBI_CLK
EBI_CLK_B
EBI_DQS_3
EBI_DQS_1
EBI_DQS_2
EBI_DQS_0
EBI_DM_3
EBI_DM_0
EBI_DM_1
EBI_DM_2
EBI_DATA_22
EBI_DATA_24
EBI_DATA_25
EBI_DATA_20
EBI_DATA_0
EBI_DATA_1
EBI_DATA_2
EBI_DATA_4
EBI_DATA_5
EBI_DATA_8
EBI_DATA_9
EBI_DATA_10
EBI_DATA_11
EBI_DATA_12
EBI_DATA_13
EBI_DATA_16
EBI_DATA_17
EBI_DATA_28
EBI_DATA_29
EBI_CS_0
EBI_DQS_3_B
EBI_DQS_2_B
EBI_DQS_0_B
EBI_DQS_1_B
EBI_DATA_3
EBI_DATA_6
EBI_DATA_7
EBI_DATA_14
EBI_DATA_15
EBI_DATA_18
EBI_DATA_19
EBI_DATA_21
EBI_DATA_23
EBI_DATA_26
EBI_DATA_27
EBI_DATA_30
EBI_DATA_31
EBI_CKE
USB_ID
RFIC0_TXBB_I_P
RFIC0_TXBB_I_N
RFIC0_TXBB_Q_P
RFIC0_TXBB_Q_N
RFIC0_PRXBB_I_P
RFIC0_PRXBB_I_N
RFIC0_PRXBB_Q_P
RFIC0_PRXBB_Q_N
GSM_PA_RAMP
WB_RX_Q_P
WB_TX_Q_N
WB_TX_Q_P
WB_RX_I_P
GPS_RX_Q_N
GPS_RX_Q_P
GPS_RX_I_N
GPS_RX_I_P
WB_RX_I_N
WB_TX_I_P
WB_TX_I_N
WB_RX_Q_N
UTXD0
URXD0
UTXD1
URXD1
<2-3-3-1-1_MT6582_DATA> Rev.0.3
0.150
0.415
0.608
0.811
R1
ADC
R2
1.114
< 9-3-1_JTAG > _DNI
Rev_0.4
140320_Changed via MTK
Memory Type : DDR2 ¡æ DDR3
140312_Changed from HDK
Close to MT6582
Close to MT6582
ESD enhance proposal. It can be cancel for cost-down proposal.
AF19 should connect to C2103 GND first than connect to GND by via.
C2103 Close to MT6582
It can be cancel for cost-down proposal.
Please reserve bypass cap for AUX_ADC decoupling (from Antenna) proposal.
R2100 0ohm deleted
REXTDN changed to NC (1/2)
1.438
0.000
1.1
100K
DNI
ADC Range(HEX.)
130K
82K
51K
30K
9.1K
R2
100K
R1
D
C
B
A
0.0
Revision
100K
100K
100K
100K
330K
1.0
100K
C2103
100N
1
2
U2100
MT6582_LPDDR3
AF19
AC1
AC2
AD2
AE2
AE1
AF1
AG2
AF2
AF4
AG4
AG5
AF5
AD6
N24
N23
R25
R26
AF26
R4
AE24
AG23
AG22
AG24
AG25
AF20
AG20
AF21
AF22
F20
E12
E17
E15
F9
B6
B7
F16
A1
M25
B3
A25
B26
C26
B25
B23
D25
A23
C24
A13
A14
D12
A11
B13
C10
A10
B11
A22
B21
D22
D20
B20
C19
A20
B19
B18
A16
A17
B16
C15
B15
D14
C14
E20
F12
F17
F15
D23
D10
D18
D16
A4
C6
D6
A5
C7
A7
A8
D8
B9
B8
B5
E9
P25
AG19
AD19
AC19
AF17
AG16
AF18
AG17
AF25
N1
R5
AF11
R2103
DNI
2
1
R2102
1.5K
TOL=0.01
R2101
5.1K
TOL=0.01
C2100
DNI
C2102
100p
C2101
100p
R2105
2
1
100K
R2106
2
1
330K
1.301
1.114
1.3
100K
100K
200K
1.2
130K
CN2100
8
7
9
6
10
5
11
4
12
3
13
2
14
1