44
Input Block
STM Block
TEC Block
LPOS Block
WBL/LPP Block
OFTR Block
OPC&ASENV
Block
RFEQ Block
JLINE Block
LOGIC Block
APC Block
MPX Block
FIN/FO2
STMO
STMON
STMOUT
SE01
SE02
TC
WBLDIF
ASENV/
LPPN
LPPS
WBL
OFTR
VPD
FPDN
SDAT
SCK
SEN
RSDAT
RSEN
EIN/FO1
CIN/TR3
DIN/TR4
AIN/TR1
BIN/TR2
HIN/TS!
GIN/TS2
VREF
CD/DVD
Switch
S/H
&
VGA
MPX
MPX
MPX
MPX
MPX
MPX
MPX
DPD Block
TCTI Block
BDO Block
FOCUS
PPTE
Block
VREF
Block
RF Gene Block
GATE
Block
Operation Circuit
SMFEP
SDAAOUT
SDABOUT
SPLAOUT
SDACOUT
SDADOUT
SPLBOUT
SRFMA
SRFMD
SRFMB
SRFMC
SNTEP
SNTEN
CHP0FT
CDFTR
SLP14
SLP23
SMFEPN
SSFEP
SSFEPN
SMTEP
SMTEN
SSTEP
SSTEN
SDAAOUT
SDABOUT
SDACOUT
SDADOUT
SDPDTEP
SRFMA
SRFMD
SRFMB
SRFMC
SDPDTEN
SPLAOUT
SPLBOUT
SPOF
TCOP
TCO
TCON
TIOP
TIO
SBDOAS
TION
LPF
VGA
VGA
COMP.
PK
ENV
PK
ENV
+
-
LPF
COMP.
VGA/
Bypass
VGA/
Bypass
M
P
X
M
P
X
DPD RE
Dielectro
TC/TI
Dielectro
HDVREF
VHALF
VREF08
RFP
CDRFP
RFN
CDRFN
BDO
RF OUT
RFIN1
RFIN2
EQOUTP
EQOUTN
VREF
GATE
All
Sum
VG
A
Grow delay
conpensation
SW
To
Each BLock
PW
ENV
VGA
COMP.
Lev1
Shift
LPF
VGA
TECENV
SLPOS2
SP23
SP11
LPF
SLPOS1
SSTEP
SSTEN
VGA
S/H
VGA
VGA
WBL
Detection
LPP
Detection
BAL
BAL
AGC/
Bypass
AGC/
Bypass
S/H
VGA
Amp
COMP.
VGA
VGA
VGA
VGA
S/H
VGA
LPF
Bypass
+
-
+
+
-
-
+
+
+
+
_
_
+
LPF
PX
ENV
BT
ENV
ATT
Amp
EQ
CPST
To
Each Block
To Each Block
To MPX
JLINE
LOGIC
COMP.
COMP.
-
VGA
VGA
VGA
VGA
S/H
S/H
S/H
LPF
LPF/
Bypass
ATT
SEL
Block Diagram