41
83, 85, 86,
88~91
FLAG_6/UA6 ~
FLAG_0/UA0
TTL I/O,
Slew rate,
50K pull-up
Internal flag monitor output.
2
nd
function : Address bus bit 6 ~ bit 0 input during address/ data
bus separated type CPU (eg. H8) application.
(FLAG_0 ~ FLAG_6)
3
rd
function : Address bus bit 11 ~ bit 13, bit 16 and bit 17 output
during IDE flash programming mode. (FLAG_0 ~
FLAG_4)
4
th
function : GPIO function.
5
th
function : External ADC interface.
For detail information, please reference to the ”ATI P Register
Definition” manual.
Crystal Interface
78
XTALI
Input
X`tal input. The working frequency is 34.5744 MHz.
79
XTALO
Output
X`tal output.
IPLL VCO Interface
104
IPLLV SS
Ground
Ground pin for IPLL VCO circuitry.
105
IPLLV DD
Analog power(5V)
Power pin for IPLL VCO circuitry.
Host Interface
92
HRST#
TTL Input, SMT,
50K pull-up
Host reset input. The active-low input is referred to as hardware
reset and is used to reset this chip.
113, 110, 108,
106, 101, 99,
96, 94, 93,
95, 98, 100,
103, 107, 109,
111
HD15 ~ HD0
TTL I/O, SMT,
Slew rate, PDR,
PPU, PPD
Host Data bus. This is the 8-bit or 16-bit bi-directional data bus to
the host. The lower 8 bits, HD0–HD7, are used for 8-bit data
transfers. Normally data transfers are 16-bit wide.
Note :
All pins except HD7 (no any pull) may be selectively
pull-up or pull-down with 20K resistant.
114
DMARQ
TTL Output
DMA request. This signal is used for DMA data transfers between
host and device and it shall be asserted by the MT1501 when it is
ready to transfer data to or from the host. The direction of data
transfer is controlled by DIOR# and DIOW#.
115
DIOW#
TTL Input, SMT,
50K pull-up
Device I/O write. Stop ultra DMA burst.
For Device I/O Write, this signal is the strobe signal asserted by
the host to write device register or the data port.
For Stop Ultra DMA, this signal shall be negated by the host before
data is transferred in an Ultra DMA burst and is asserted by host
during an Ultra DMA burst to signal the termination of Ultra DMA
burst.
116
DIOR#
TTL Input, SMT,
50K pull-up
Device I/O read. Ultra DMA ready. Ultra DMA data strobe.
For Device I/O Read, this signal is the strobe signal asserted by
the host to read device registers or the data port.
For Ultra DMA ready, this is asserted by the host to indicate to the
device that the host is ready to receive Ultra DMA data in burst to
the host.
For Ultra DMA data strobe, this signal is the data out strobe signal
from the host for an Ultra DMA data out burst