LG Chocolate KE800, Service Manual, Page: 84 / 142

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VBAT
PWR
URXD
UTXD
3G 2.5G
GND
RX
TX
UFLS
ON_SW
D
10
4
Drawn by:
INTEL Memory(1Gbit NOR+128SDRAM, 1.8 I/O)
9
DIGD
6
DIGD
B
F
LG Electronics
C
DIGA
5
DIGC1~2
Drawing Number:
C
7
G
Changed by:
Capulet
N/A
0 Ohm
0 Ohm
10 7
3
RTC
DOC CTRL CHK:
11
BASE BAND PROCESSOR
DIGD
Modified
Sibely
DIGA
Modified
3
REV:
N/A
M
DIGB
ON BOARD ARM9 JTAG & ETM INTERFACE
E
R109
12
MFG ENGR CHK:
Engineer:
B
R107
6
VBR
9 2
DIGD
8
Size:
MMC
12
DIGA
DIGD
1
Date Changed:
2
Modified
DIGA
Time Changed:
H
5
11
A
QA CHK:
USB
F
DIGC2
1
A3
12 1 8 A
Modified
DIGA
E
DIGC1~2
DIGD
TITLE:
BB
Page:
H
B
4
ETM
SIM
8
RTC
DIGC2
REV-1.2
DIGC1
EBU
DIGD
G
PLL
A
DIGC1
R&D CHK:
BB
RTC
D
mentor 2006-04-07 3:07:35 pm 1/5
KE800
2V65_ANA
TP112
2V85_SIM
0.1u
C117
SN74AUC1G08YZPR U102
GND
C1
A1
B1
C2
A2
VCC
R107 NA
0 R110
TP107 1V8_MEM
R113
22
R108
3.3K
R134 4.7K
C113
0.1u
1V8_MEM
R111 0
NA R114
1u
1V8_MEM
TP106
C116 C110
0.1u 1u
C109
0.1u
C128
R115 15K
C123
1V5_DSP
0.1u
1V5_DSP
NA
R131
C127
0.1u
22 R121
100K
R109
0.1u
C108
TP103
0.1u
C122
3300
R120
R122 22
32.768KHz
X101
1 2
0 R124
C107
0.1u
C136
1V8_MEM
0.1u
1V5_CORE
C126
0.1u
R119 2.7K
2.7K R117
2V72_IO
2V72_IO
TP101
0.1u
R112 22
C130
6
VBAT
0.1u
C115
UA101
12
CTS
10
DSR
1
GND
4
NC1
NC2
7
8
NC3
NC4
9
ON_SW
5
RTS
11
2
RX
TX
3
0.1u
C134
TP111
R123 0
R132 4.7K
TP105
C106
0.1u
100K
1V8_MEM
R118
C105
0.1u
TP104
C131 220n
3V1_USB
4.7
R103
0
R102
0.1u
C125
0.01u
C111
C104
0.1u
1V8_MEM 1V5_CORE
0.1u
C102
0.1u
C101
C129
0.1u
P5
VSSP_ETM
T17
VSSVBR_1
VSSVBR_2
P17
VSSVBT
R16
VSS_DSPMAIN1
J8
VSS_DSPMAIN2
J9 J10
VSS_DSPMAIN3
J11
VSS_DSPMAIN4 VSS_DSPMAIN5
L8
VSS_DSPMAIN6
L9 L10
VSS_DSPMAIN7
L11
VSS_DSPMAIN8
VSS_PLL_RTC
T12 R12
VSS_USB
W11
VDD_USB
K16
VMICN VMICP
L16
P16
VREFN
L17
VREFP
VSSBB
L15
N19
VSSBG
U16
VSSD
V15
VSSM
VSSP_DIG1
J15 E13
VSSP_DIG2
E10
VSSP_DIG3 VSSP_DIG4
E8 J5
VSSP_EBU1 VSSP_EBU2
M5
VSSP_EBU3
R8
VDDP_MMC
A13 L19
VDDP_SIM
U18
VDDVBR_1
VDDVBR_2
R17
T15
VDDVBT
VDD_DSP1
H9 H10
VDD_DSP2
H11
VDD_DSP3
M9
VDD_MAIN1 VDD_MAIN2
M10
VDD_MAIN3
K8 K9
VDD_MAIN4
K10
VDD_MAIN5 VDD_MAIN6
K11
VDD_PLL
W12 W13
VDD_RTC
D9
USIF_SCLK USIF_TXD_MTSR
A7
VCXO_EN
K19
M15
VDDBB
VDDBG
K17
VDDD
T14
VDDM
V14
VDDP_DIGA
G19
VDDP_DIGB
A9 A15
VDDP_DIGC1
B19
VDDP_DIGC2
VDDP_DIGD
B1
VDDP_EBU1
J1
VDDP_EBU2
W2 W7
VDDP_EBU3
W10
VDDP_ETM
C18
T_OUT5
T_OUT6
D15
T_OUT7
D14
A18
T_OUT8
T_OUT9
C14
G3
USART0_CTS_N USART0_RTS_N
H4
USART0_RXD
G1 G4
USART0_TXD
F15
USART1_CTS_N USART1_RTS_N
E19
USART1_RXD
F17 G18
USART1_TXD
USB_DMINUS
V11
U11
USB_DPLUS
USIF_RXD_MRST
B7
TRACEPKT3
V9
U10
TRACEPKT4
TRACEPKT5
V10
R10
TRACEPKT6
TRACEPKT7
T11
U8
TRACESYNC
TRIG_IN
E14
TRST_N
C19
T_OUT0
B17
B16
T_OUT1
A16
T_OUT10
T_OUT11
C13
D17
T_OUT12
T_OUT2
B15
D13
T_OUT3
T_OUT4
B14
C17
RF_STR0
RF_STR1
A17
F18
RSTOUT_N
D18
RTCK
V12
RTC_OUT
SSC1_MRST
J17 K18
SSC1_MTSR
H15
SSC1_SCLK
E16
TCK
TDI
D19
E17
TDO
F16
TMS
TRACECLK
V8
R9
TRACEPKT0
TRACEPKT1
W9
T10
TRACEPKT2
U15
NC6
R11
NC7
L5
NC8
H5
NC9
V13
OSC32K
L12
PAOUT1A
PAOUT1B
M11
K12
PAOUT2A
PAOUT2B
J12
T9
PIPESTAT0
PIPESTAT1
U9
PIPESTAT2
W8
PM_INT
T13
RESET_N
U14
B18
RF_CLK
C16
RF_DATA
P19
MICN2
M17
MICP1 MICP2
N18
MMCI_CLK
C11
E12
MMCI_CMD
MMCI_DAT0
C12
D12
MMCI_DAT1
MMCI_DAT2
B12
MMCI_DAT3
A12
B13
MON1
MON2
A14
NC1
W19
NC2
W14 W1
NC3
A19
NC4 NC5
A1
F5
KP_IN3 KP_IN4
E3
KP_IN5
E2 E1
KP_IN6
D3
KP_OUT0 KP_OUT1
F4
KP_OUT2
C2 C1
KP_OUT3
M0
U17
W17
M1
M10
W18
M2
W16
W15
M7
M8
V16
V17
M9
MICN1
M18
I2S1_CLK1
G16
I2S1_RX
G17 G15
I2S1_TX
E18
I2S1_WA0 I2S2WA0
J19
I2S2WA1
H16
I2S2_CLK0
J18
I2S2_CLK1
H17 H19
I2S2_RX
H18
I2S2_TX
B2
IRDA_RX
IRDA_TX
A2
IREF
M16
KP_IN0
D2
KP_IN1
D1 D5
KP_IN2
P18
EPN11 EPN12
N17
EPP11
R19 T19
EPP12 EPPA11
T18 R18
EPPA12
V18
EPPA2
V19
EPREF1 EPREF2
U19
U12
F26M
F32K
U13
FCDP_RB_N
G2
K15
GUARD
C3
I2C_SCL
E4
I2C_SDA
F19
I2S1_CLK0
M3
EBU_BC0_N
EBU_BC1_N
P2
V3
EBU_BFCLKI
EBU_BFCLKO
R3
EBU_CAS_N
M4
EBU_CKE
T3
P4
EBU_CS0_N
EBU_CS1_N
V1
T2
EBU_CS2_N
P3
EBU_CS3_N
M2
EBU_RAS_N
EBU_RD_N
N3
U4
EBU_SDCLK1
EBU_SDCLKO
U3
EBU_WAIT_N
T6
U1
EBU_WR_N
R4
EBU_AD1
V6
EBU_AD10
EBU_AD11
W6
T8
EBU_AD12
EBU_AD13
U7
V7
EBU_AD14
EBU_AD15
R7
EBU_AD2
W3
T5
EBU_AD3
EBU_AD4
R6
U5
EBU_AD5
EBU_AD6
W4
W5
EBU_AD7
EBU_AD8
U6
EBU_AD9
V5
T7
EBU_ADV_N
EBU_A18
N2
N4
EBU_A19
EBU_A2
J4
EBU_A20
N5
T1
EBU_A21
EBU_A22
R2
U2
EBU_A23
V2
EBU_A24
J2
EBU_A3
J3
EBU_A4
EBU_A5
K1
K2
EBU_A6
EBU_A7
K3
K5
EBU_A8
EBU_A9
L2
EBU_AD0
V4
B3
DIF_VD
A3
DIF_WR
F3
DSP_IN0 DSP_IN1
G5
DSP_OUT0
F1 F2
DSP_OUT1
EBU_A0
H2
H3
EBU_A1
L1
EBU_A10
EBU_A11
M1
N1
EBU_A12
EBU_A13
K4
EBU_A14
L4
P1
EBU_A15
EBU_A16
L3
R1
EBU_A17
CLKOUT0
H1
DIF_CD
B5
DIF_CS1
A4 E6
DIF_CS2 DIF_D0
A6 C7
DIF_D1
B6
DIF_D2 DIF_D3
D8
DIF_D4
E7 A5
DIF_D5
D7
DIF_D6 DIF_D7
C6
DIF_HD
B4
DIF_RD
C5 D6
DIF_RESET1 DIF_RESET2
C4
L18
CC_IO
M19
CC_RST
E11
CIF_D0
B11
CIF_D1 CIF_D2
C10
CIF_D3
A11 D11
CIF_D4
B10
CIF_D5 CIF_D6
A10
CIF_D7
B9 A8
CIF_HSYNC
C9
CIF_PCLK
B8
CIF_PD
C8
CIF_RESET CIF_VSYNC
D10
CLKOUT
E9
PMB8876
U103
AFC
C15
AGND
N16
BB_I
R13
R14
BB_IX
P15
BB_Q
N15
BB_QX
CC_CLK
J16
0.1u
1V8_MEM
C120
NA
R128
2V11_RTC
TP102
22K R125
C135
C133
0.1u
22p
R116 NA
R101
0
C114 C124
0.01u 0.1u
C132
22p
G1 G2
G3 G4
0.1u
C103
9
16
25
26
27
28
29
30
17
18
19
20
21
22
23
24
1
10
11
12
13
14
15
2
3
4
5
6
7
8
_F_RST
G7
E1
_F_WP1
F1
_F_WP2
H7
_OE
F6
_S_CS1
_WE
E2
CN101
C7
VSS5
VSS6
C8
VSS7
K2
K3
VSS8
VSS9
K4
_D1_CS
F2
_D2_CS
E3
_D_CAS
F3
H5
_D_CLK
F4
_D_RAS
_D_WE
H6
G3
_F1_CE
_F2_CE
G2
_F3_CE
H3
E6
_F4_CE_A27
_F_ADV
D5
N_CLE
E5
H1
N_RY__BY
RFU
G1
S_CS2
H2
D2
S_VCC
J2
VCCQ1
VCCQ2
J3
VCCQ3
J7
VCCQ4
J8
VSS1
C2
VSS10
K6
K7
VSS11
VSS12
K8
C3
VSS2
VSS3
C4
VSS4
C6
H9
D_DM0__S_LB
H8
D_DM1__S_UB
M3
D_LDQS
D_UDQS
M7
C5
D_VCC1
D_VCC2
D3
D_VCC3
D7
K5
F_CLK
F_DPD
B6
D4
F_VCC1
D6
F_VCC2
J4
F_VCC3
J6
F_VCC4
F_VPP
J1
F_WAIT
J9
N_ALE
D8
K1
DQ2
L2
DQ3
DQ4
M4
DQ5
L3
DQ6
L4
DQ7
L5
M5
DQ8
L6
DQ9
DU1
A1
DU2
A9
M1
DU3
DU4
M9
G4
D_BA0
D_BA1
H4
D_CKE
G6
D_CLK
J5
A26
B8
A3
B2
A2
A4
A5
B3
A3
A6
A4
A7
A8
G8
A9
F8
DQ0
M2
DQ1
L1
DQ10
M6
DQ11
L7
L8
DQ12
K9
DQ13
DQ14
L9
DQ15
M8
A11
G9
F9
A12
E9
A13
D9
A14
A15
C9
B9
A16
B4
A17
B5
A18
A19
A5
B1
A2
F7
A20
E7
A21
B7
A22
A23
A6
A24
A7
A8
A25
PF38F5570MMY0B0 U101
D1
A0
A1
C1
A10
E8
NA
R129
VSUPPLY
390K
R106
2V85_CARD
C112
1u
C118
0.01u
2V72_IO
C121
0.01u
22K
R105
TP?
TP?
TP?
2V72_IO
C119
1u
1V8_MEM
TP108
R104
NA
_FLASH1_CS
_FLASH2_CS
_1G_CS
DIF_VSYNC
VMICN VMICP
TOUCH_EN
EL_KEY_BACKLIGHT
TOUCH_INT
RF_TEMP
VCXO_EN
CIF_MCLK
BFCLKO
SDCLKO
TF_PWR_EN
_FLASH1_CS
_FLASH2_CS
_FLASH1_CS
_1G_CS
CHG_EOC
SLIDE_DETECT
LCD_ID
JACK_TYPE
RCV_P
_ADV
_BC0
_BC1
RPWRON
ANT_SW3
MON2
FM_INT
CAM_PWR_EN
_FM_RESET
FM_BBP_SEL
KP_OUT(4)
REMOTE_INT
MIC_PATH_SEL
A(14)
A(13)
TOUCH_DAT
LCD_DIM_CTRL
_CHG_EN
TRACEPKT(0)
TRACEPKT(1)
TRACEPKT(2)
TRACEPKT(3)
TRIG_OUT
_TRST
TDI
TMS
TCK
RTCK
TDO
_EXTRST
TRIG_IN
TRACEPKT(7)
TRACEPKT(0:7)
MON1
BFCLKI
_WP
SDCLKI
_RESET
A(0:24) D(0:15)
TRACEPKT(4)
TRACEPKT(5)
TRACEPKT(6)
TRACECLK
TRACESYNC
PIPESTAT0
PIPESTAT1
PIPESTAT2
D(6)
D(7)
D(8)
D(9)
CKE
F_DPD
_WAIT
_RAM_CS
_CAS
_RAS
_WR
_RD
A(6)
A(7)
A(8)
A(9)
D(0)
D(1)
D(10)
D(11)
D(12)
D(13)
D(14)
D(15)
D(2)
D(3)
D(4)
D(5)
A(13)
A(14)
A(15)
A(16)
A(17)
A(18)
A(19)
A(2)
A(20)
A(21)
A(22)
A(23)
A(24)
A(3)
A(4)
A(5)
TRACEPKT(0)
TRACEPKT(1)
TRACEPKT(2)
TRACEPKT(3)
TRACEPKT(4)
TRACEPKT(5)
TRACEPKT(6)
TRACEPKT(7)
C_FLASH
F_DPD
DIF_RD
_BT_RESET
DIF_CD TOUCH_CLK
MON1
HOOK_DETECT
A(0)
A(1)
A(10)
A(11)
A(12)
CIF_D(2) CIF_D(1) CIF_D(0)
USIF_TXD USIF_RXD
TX_DEBUG RX_DEBUG
TXD_0 RXD_0 RTS_0 CTS_0
CLK32K KP_IN(5)
PM_INT
_SIM_EN
TOUCH_LED_EN
CIF_PD
TRIG_OUT DSR
TRACEPKT(0:7)
A(0:24)
DIF_D(7) DIF_D(6) DIF_D(5) DIF_D(4) DIF_D(3) DIF_D(2) DIF_D(1) DIF_D(0)
CIF_D(7) CIF_D(6) CIF_D(5) CIF_D(4) CIF_D(3)
RPWRON_EN
RXD_0
RTS_0
DSR
TXD_0
VSUPPLY
D(0:15)
DIF_D(0:7)
CIF_D(0:7)
AFC
SDCLKO
BFCLKO
I_MONITOR
CTS_0
ANT_SW2
MODE
JACK_DETECT
USB_DM
USB_DP
VCXO_EN
PA_LEVEL
PIPESTAT0
PIPESTAT1
PIPESTAT2
_RESET
RF_CLK
RF_DA
RF_EN
TF_DETECT
RTCK
RTC_OUT
TCK
TDI
TDO
TMS
TRACECLK
TRACESYNC
TRIG_IN
_TRST
TXON_PA
VIBRATOR_EN
PA_BAND
ANT_SW1
KP_OUT(2) KP_OUT(3)
BATT_TEMP
REMOTE_ADC
MIC1_N MIC2_N MIC1_P MIC2_P
TF_CLK
TF_CMD
TF_DAT0
TF_DAT1
TF_DAT2
TF_DAT3
MON2
26MHZ_MCLK
SCL SDA
I2S1_CLK
I2S1_RX I2S1_TX I2S1_WA
_WP
KP_IN(0) KP_IN(1) KP_IN(2) KP_IN(3) KP_IN(4)
KP_OUT(5) KP_OUT(0) KP_OUT(1)
D(2)
D(3)
D(4)
D(5)
D(6)
D(7)
D(8)
D(9)
_ADV
_BC0
_BC1
BFCLKI
_CAS
CKE
_FLASH1_CS
_RAM_CS
_FLASH2_CS
_RAS
_RD
SDCLKI
_WAIT
_WR
RCV_N
BBP_SND_L BBP_SND_R
A(10)
A(11)
A(12)
A(13)
A(14)
A(15)
A(16)
A(17)
A(18)
A(19)
A(2)
A(20)
A(21)
A(22)
A(23)
A(24)
A(3)
A(4)
A(5)
A(6)
A(7)
A(8)
A(9)
D(0)
D(1)
D(10)
D(11)
D(12)
D(13)
D(14)
D(15)
I
IX
Q
QX
SIM_CLK
SIM_IO
SIM_RST
CIF_HS
CIF_PCLK
CIF_RESET
CIF_VS
DIF_CS
DIF_RESET
DIF_WR
A(0)
A(1)
7. CIRCUIT DIAGRAM