LG Chocolate KE800, Service Manual, Page: 21 / 142

3. TECHNICAL BRIEF
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3.5 Baseband Chip(PMB8876, U101)
(1) Introduction
PMB8876 is a GSM/EDGE single chip mixed signal baseband IC containing all analog and digital
functionality of a cellular radio. Additionally PMB8876 provides multimedia. It is operated as a single chip
solution, integrating the digital and mixed signal portions of the base band.
Processing cores
- ARM926EJ-S 32 bit processor core for controller functions. The ARM926EJ-S includes an MMU, and the
Jazelle Java extension for Java acceleration.
- TEAKLite® DSP core.
ARM-Memory
- 32 kByte Boot ROM on the AHB.
- 96 kByte SRAM on the AHB, flexibly usable as program or data RAM
- 16 kByte cache for program (internal)
- 8 kByte tightly coupled memory for program (internal)
- 8 kByte cache for data (internal)
- 8 kByte tightly coupled memory for data (internal)
TEAKLigh ® t-Memory
- 104k X 16bit Program ROM
- 8k X 16bit Program RAM
- 60k X 16bit Data ROM
- 37k X 16bit Data RAM
- Incremental Redundancy (IR)Memory of 35904 words of 16 bit
Shared Memory Block
- 1.5k X 32bit Shared RAM (dual ported) between controller system and TEAKLite ®
Controller Bus System
The processing cores and their peripherals are connected by powerful buses:
- multi-layer AHB for connecting the ARM and the other master capable building blocks with the internal and
external memories and with the peripheral buses.
- 1FPI-Bus for connecting the controller peripherals which require DMA support, called hereafer FPI1
respectively.
- An FPI-Bus for connecting GSM peripherals, called hereafter FPI3 bus.
- A controller FPI Bus for connecting the low performance controller peripherals such as keypad etc.,called
hereafter FP12 bus.
- FPI1, FPI2 and FPI3 are connected asynchronously to the AHB buses. 1DMA controller with 8 channels
releases the controller from data transfers.
- 1 AHB Lite-bus for connecting multimedia and high performance peripherals, called AHB_PER hereafter.
This peripheral bus is connected to the multilayer AHB’Backbone’ by an asynchronous, bust capable
AHB2AHB bridge which is shared between accessing masters.
- The DMA controller is enabled to access AHB_PER by the use of its second master interface.