39
Pin No.
Pin Name
Type
Description
67
DMACK#
I/O
ATA DMA Acknowledge/DMA Request : ATAPI DMA acknowledge
DMA request when connected to SCSI controller
IORDY/
68
DDMARDY#/
O
TS
ATA Host I/O Ready : I/O channel ready
DSTROBE
UDMA : DDMARDY#, device DMA ready; DSTROBE, device data strobe
HRD#/
69
HDMARDY#/
I/O
PUA
ATA Host Read Strobe/SCSI DMA Read Strobe
HSTROBE
UDMA : HDMARDY#, host DMA ready; HSTROBE, host data strobe
70
HWR#/
I/O
PUA
ATA Host Write Strobe/SCSI DMA Write Strobe
STOP
UDMA : Host stop
131
ARST
O
TS
ATAPI Reset
SYSTEM CONTROLLER Interface
Pin No.
Pin Name
Type
Description
95
PRST#
I
S
System Reset : Internal state machines are reset and all registers are set to
default. The assertion and negation signal of PRST# can be ASYNC to XIN but
needs to be longer then 1 XIN, because the signal goes through a de-glitch circuit.
106
UCS0#
I
S
Chip Select 0 : Enables access to internal registers
107
UCS1#
I
S
Chip Select 1 : Enables access to buffer memory
Read Enable/Data Strobe : Read enable/data strobe input for read
104
URD#
I
S
If CPUTYPE = VCC (Intel) – This pin is read enabled.
If CPUTYPE = GND (Motorola) – This pin is data strobe.
Write Enable/Data read Status : Write enable/data read write status input for read
105
UWR#
I
S
If CPUTYPE = VCC (Intel) – This pin is write enabled.
If CPUTYPE = GND (Motorola) – This pin is read/write status.
110
URDY
I/O
PU
Ready : Data ready
Select use/no use by setting internal registers
When accessing internal registers or buffer memory, this signal is asserted after
fixing driven data.
If no access, this pin is Hi-Z.
Hi-Z status at reset.
113
SDINT#
SDINT# : CD-DSP and CD-Servo system input.
112
UINT1#
O
PU
System Interrupt Request 1 & 0 : CD-Decoder/-Encoder interrupt Signals
111
UINT0#
selected by bits INTSEL4-0 in the INTMODE Register (005h,4-0)
103
UAD7
102
UAD6
101
UAD5
I/O
Address and Data : Address and data are multiplexed in the same pin.
100
UAD4
If I/O only data, fix UALE to GND.
99
UAD3
These Signals ARE Hi-Z when chip is reset.
98
UAD2
97
UAD1
96
UAD0