3. TECHNICAL BRIEF
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3.6 MEMORY(M36W0R5040U62S, U102 )
The M36W0R5040U62S combine two memory devices in a multichip package:
- a 32-Mbit or 64-Mbit, multiple bank flash memory, the M58WR0xxKUL
- a 16-Mbit pseudo SRAM, the M69KM024A
Collectively, these four devices are referred to in this document as the M36W0Rx040x6.
The purpose of this document is to describe how the two memory components operate with
respect to each other. It must be read in conjunction with the M58WR0xxKUL and
M69KM024A datasheets, which detail all the specifications required to operate the flash
memory and PSRAM components. These datasheets are available from your local
Numonyx distributor.
The memory is offered in a stacked TFBGA52 (6 x 4 mm, 10 x 6 ball array, 0.50 mm pitch)
package. Recommended operating conditions do not allow more than one memory to be
active at the same time.
Figure. 3.6.1 MEMORY BLOCK DIAGRAM
3. TECHNICAL BRIEF
