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LG Electronics Inc. All rights reserved.
Only for training and service purposes.
BLOCK DIAGRAM
1. Main IC
Main IC
eMMC (4GB)
USB1 (2
.0)
OCP
USB2 (2
.0)
HDM
I3
HDM
I2(A
RC)
HDM
I1
Cable
TUNE
R
TUNER
ATSC3.0 F-
NIM
tuner
CVBS
SIF
MI
COM
IR
/ KEY
USB_WI
FI
X_
TAL
27MHz
Sub Assy
LAN
ETHERNET
SPDIF
AV/COMP
CVBS/YPbPr
SPDIF OUT
H/P
AMP
RS-232
MAX323
MA
IN
Audio
AM
P
I2S
Out
I2
C
4
Vx
1 51P
(8 lane)
Vx
1
/ EPI
/ CEDS
FCIC
SP
I/
I2C
6
Ma
in
PM
IC
M0
M1
IF
CVBS
/SIF
GST/
MC
LK/GCLK/EO
/I2C
6
NVRAM
(256Kb)
I2
C_1
I2
C 2
EPI
bloc
k
HDM
I4
TS
DDR3
2133
X
32
(256
MB
X
2EA)
DDR3
2133
X
32
(512
MB
X
2EA)
N/
A
[EPI
60P
(65”:8 lane,
55”
↓:
6 la
ne),
CEDS 68P]
Area
OPT
USB_
WI
FI
I2
C_SDA_1
1.5V
DDR
0.95
V
Core&CPU
3.3V
Norm
al
1.0V
Eth
3.5V
ST_BY
1.8V
5V
Norm
al
Sub PM
IC
0.
95
V
1.
5V
3.
3V
5V
1V
1.
8V
3.
5V
_S
T
0.
95
V
1.
5V
3.
3V
3.
3V
5V
1V
1.
8V
1.
8V
3.
5V
_S
T
3.
5V
_S
T
3.
3V
3.
5V
_S
T
3.
5V
_S
T
13
V
3.
5V
_S
T
13
V
3.
5V
_S
T
13
V
3.
3V
13
V
13
V
3.
3V
13
V(
PA
NE
L_
VC
C)
13
V(
PA
NE
L_
VC
C)
To
Pa
ne
l
From
Power B/D
13
V
To
W
IF
I/B
T
Co
m
bo
Ai
r
IF+/-
Summary of Contents for 70UM6970PUA
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