LG 60LN549E, Service Manual

Page: 64 / 67

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
PWM0_CONFIG
TXD0N
10K
R9615
+1.26V_FRC
FRC_DDR3_RESETB
TXA4P
0 . 1 u F
C9607
DVDD_DDR_1V
0 . 1 u F
C9615
FRC_DQSL
SCL2_+3.3V_DB
TXB1P
0 . 1 u F
C9600
10K
OPT
R9603
FRC_ODT
TXA3P
SDA2_+3.3V_DB
FRC_VDD33
+3.3V_FRC
FRC_MCK
TXB2N
0 . 1 u F
C9631
0 . 1 u F
C9606
TXCCLKP
0 . 1 u F
C9632
FRC_DQSU
+3.3V_FRC
BLM18SG121TN1D
L9603
FRC_AVDD_LVDS33
10K
R9610
+1.5V_FRC_DDR
FRC_CASB
FRC_DQSUB
FRC_AVDD_PLL
0 . 1 u F
C9626
TXD4N
GPIO[1]
22uF
10V
C9611
0
R9641
OPT
PWM0_CONFIG
3.3K
R9653
FRC_DMU
PWM1_CONFIG
URSA_MODEL_OPT_1
TXD2P
+3.3V_FRC
FRC_MCKB
SPI_SCLK
GPIO[1]
FRC_DQSLB
10K
OPT
R9613
33
R9652
TXB0P
TXA1P
FRC_A[0-13]
SCL2_+3.3V_URSA
TXA4N
GPIO[8]
0 . 1 u F
C9603
10K
OPT
R9608
TXACLKN
TXC3N
FRC_DQU[0-7]
10K
OPT
R9611
22 R9600
URSA5_DEBUG
FRC_AVDD_PLL
0 . 1 u F
C9618
TXD2N
0
R9618
URSA5_MP
+3.3V_FRC
FRC_DML
URSA_MODEL_OPT_0
JS2235S
SW9600
URSA5_DEBUG
3
2
1
4
5
6
SPI_SCLK
TXCCLKN
FRC_AVDD_LVDS33
10K
OPT
R9614
0
R9620
URSA5_MP
TXBCLKP
BLM18SG121TN1D
L9605
URSA_MODEL_OPT_0
FRC_AVDD_PLL
TXD1P
+3.3V_Normal
0 . 1 u F
C9605
SPI_DI
URSA_MODEL_OPT_3
+1.26V_FRC
TXA2N
10K
R9602
10K
OPT
R9616
SPI_DI
FRC_WEB
33 R9637
SPI_CS
TXB4N
GPIO[8]
TXC3P
FRC_VDDC10
TXD0P
TXC0N
0 . 1 u F
C9612
TXD1N
TXA0N
0 . 1 u F
C9609
SPI_DO
FRC_VDD33
FRC_CKE
URSA_MODEL_OPT_3
0 . 1 u F
C9602
TXB2P
TXB3P
FRC_VDDC10
10uF
6.3V
C9614
0 . 1 u F
C9628
10K
R9650
URSA_SDA
AFRC_VDD33
SDA2_+3.3V_URSA
TXD3P
0 . 1 u F
C9604
0 . 2 2 u F
6.3V
C9619
0 . 1 u F
C9616
SCL2_+3.3V_URSA
0 . 1 u F
C9625
TXA1N
0 . 1 u F
C9630
0 . 1 u F
C9622
0.1uF
C9634
URSA_MODEL_OPT_2
FRC_AVDD_LVDS33
TXC4P
TXA0P
BLM18SG121TN1D
L9601
+3.3V_FRC
AFRC_VDD33
0 . 1 u F
C9620
TXC2N
33 R9622
LGE7303C
IC9600
DDR3_A0/DDR2_NC
P14
DDR3_A1/DDR2_A8
G15
DDR3_A2/DDR2_NC
N14
DDR3_A3/DDR2_A10
L15
DDR3_A4/DDR2_A2
H15
DDR3_A5/DDR2_A3
L14
DDR3_A6/DDR2_A4
G14
DDR3_A7/DDR2_A5
N12
DDR3_A8/DDR2_A6
G13
DDR3_A9/DDR2_A9
N13
DDR3_A10/DDR2_RASZ
H14
DDR3_A11/DDR2_A11
F15
DDR3_A12/DDR2_A0
H13
DDR3_A13/DDR2_A12
P13
DDR3_BA0/DDR2_BA2
M12
DDR3_BA1/DDR2_CASZ
H12
DDR3_BA2/DDR2_A1
L13
DDR3_MCLK/DDR2_MCLK
F16
DDR3_MCLKZ/DDR2_MCLKZ
F17
DDR3_CKE/DDR2_ODT
J 1 3
DDR3_ODT/DDR2_CKE
K12
DDR3_RASZDDR2_WEZ
L12
DDR3_CASZ/DDR2_BA1
K13
DDR3_WEZ/DDR2_BA0
K14
DDR3_RESET/DDR2_A7
M14
DDR3_DQSL/DDR2_DQSL
N16
DDR3_DQSU/DDR2_DQSU
M17
DDR3_DQSBL/DDR2_DQSBL
M16
DDR3_DQSBU/DDR2_DQSBU
M15
DDR3_DQML/DDR2_DQU5
J 1 5
DDR3_DQMU/DDR2_DQU4
R16
DDR3_DQL0/DDR2_DQU3
R17
DDR3_DQL1/DDR2_DQL0
H17
DDR3_DQL2/DDR2_DQL6
R15
DDR3_DQL3/DDR2_DQL7
J 1 7
DDR3_DQL4/DDR2_DQL3
T17
DDR3_DQL5/DDR2_DQL2
H16
DDR3_DQL6/DDR2_DQL1
T15
DDR3_DQL7/DDR2_DQL5
G16
DDR3_DQU0/DDR2_DQU7
K15
DDR3_DQU1/DDR2_DQML
N15
DDR3_DQU2/DDR2_DQU2
K17
DDR3_DQU3/DDR2_DQU6
P17
DDR3_DQU4/DDR2_NC
L17
DDR3_DQU5/DDR2_DQU1
P16
DDR3_DQU6/DDR2_DQU0
K16
DDR3_DQU7/DDR2_DQMU
P15
I2CM_SCL
D14
I2CM_SDA
D15
I2CS_SCL
P1
I2CS_SDA
P2
DDR3_NC/DDR2_A13
F14
DDR3_NC/DDR2_DQL4
T16
VSS_1
D6
VSS_2
D7
VSS_3
D8
VSS_4
D9
VSS_5
E6
VSS_6
E7
VSS_7
E8
VSS_8
E9
VSS_9
E10
VSS_10
E16
VSS_11
F3
VSS_12
F6
VSS_13
F7
VSS_14
F8
VSS_15
F9
VSS_16
G1
VSS_17
G2
VSS_18
G4
VSS_19
G5
VSS_20
G6
VSS_21
G7
VSS_22
G8
VSS_23
G9
VSS_24
G17
VSS_25
H1
VSS_26
H2
VSS_27
H4
VSS_28
H5
VSS_29
H6
VSS_30
H7
VSS_31
H8
VSS_32
H9
VSS_33
H10
VSS_34
H11
VSS_35
J4
VSS_36
J5
VSS_37
J6
VSS_38
J7
VSS_39
J8
VSS_40
J9
VSS_41
J10
VSS_42
J11
VSS_43
J12
VSS_44
J14
VSS_45
J16
VSS_46
K4
VSS_47
K5
VSS_48
K6
VSS_49
K7
VSS_50
K8
VSS_51
K11
VSS_52
L6
VSS_53
L7
VSS_54
L8
VSS_55
L11
VSS_56
L16
VSS_57
M6
VSS_58
M7
VSS_59
M8
VSS_60
M11
VSS_61
M13
VSS_62
N6
VSS_63
N7
VSS_64
N8
VSS_65
N17
VSS_66
P3
VSS_67
P4
VSS_68
P5
VSS_69
P6
VSS_70
P7
VSS_71
P12
VSS_72
U16
NC
L9
HW_RESET
J3
TESTPIN_1
D1
TESTPIN_2
D2
TESTPIN_3
D3
TESTPIN_4
E1
TESTPIN_5
E2
TESTPIN_6
E3
TESTPIN_7
F1
TESTPIN_8
F2
M0_SCLK
C17
M0_MOSI
D16
M1_SCLK
D17
M1_MOSI
E15
M2_SCLK
E14
M2_MOSI
E13
M3_SCLK
E12
M3_MOSI
F13
SPI_CK
T9
SPI_CZ
U10
SPI_DI
U9
SPI_DO
T10
TXA0P/GCLK6/BLUE[7]
C8
TXA0N/GCLK5/BLUE[6]
C9
TXA1P/OPT_N/LK3/BLUE[9]
B8
TXA1N/FLK/BLUE[8]
A8
TXA2P/GREEN[1]
A7
TXA2N/OPT_P/LK2/GREEN[0]
B7
TXACLKP/RLV0N/GREEN[3]
C6
TXACLKN/RLV0P/GREEN[2]
C7
TXA3P/RLV1N/GREEN[5]
B6
TXA3N/RLV1P/GREEN[4]
A6
TXA4P/RLV2N/GREEN[7]
A5
TXA4N/RLV2P/GREEN[6]
B5
TXB0P/RLV3N/GREEN[9]
C4
TXB0N/RLV3P/GREEN[8]
C5
TXB1P/RLVCLKN/RED[1]
B4
TXB1N/RLVCLKP/RED[0]
A4
TXB2P/RLV4P/RED[3]/EPI_A3P
A3
TXB2N/RLV4N/RED[2]/EPI_A3N
B3
TXBCLKP/RLV5N/RED[5]/EPI_A2P
C2
TXBCLKN/RLV5P/RED[4]/EPI_A2N
C3
TXB3P/RLV6N/RED[7]/EPI_A1P
B2
TXB3N/RLV6P/RED[6]/EPI_A1N/
A2
TXB4P/RLV7N/RED[9]/EPI_A0P
C1
TXB4N/RLV7P/RED[8]/EPI_A0N
B1
TXC0P/SOE
C16
TXC0N/POL
B17
TXC1P/GSP_R
B16
TXC1N/GSP/VST
A16
TXC2P/GOE/GCLK1
A15
TXC2N/GSC/GCLK3
B15
TXCCLKP/LLV0N
C14
TXCCLKN/LLV0P
C15
TXC3P/LLV1N
B14
TXC3N/LLV1P
A14
TXC4P/LLV2N
A13
TXC4N/LLV2P
B13
TXD0P/LLV3N
C12
TXD0N/LLV3P
C13
TXD1P/LLVCLKN
B12
TXD1N/LLVCLKP
A12
TXD2P/LLV4N/EPI_B3P
A11
TXD2N/LLV4P/EPI_B3N
B11
TXDCLKP/LLV5N/BLUE[1]/EPI_B2P
C10
TXDCLKN/LLV5P/BLUE[0]/EPI_B2N
C11
TXD3P/LLV6N/BLUE[3]
B10
TXD3N/LLV6P/BLUE[2]/EPI_B1N
A10
TXD4P/LLV7N/BLUE[5]/EPI_B0P
A9
TXD4N/LLV7P/BLUE[4]/EPI_B0N
B9
MOD_GPIO0/VDD_ODD/HSYNC
D10
MOD_GPIO1/VDD_EVEN/VSYNC
D11
MOD_GPIO2/PWM13/GCLK4/LCK
D12
MOD_GPIO3/PWM14/GCLK2/LDE
D13
PWM0/SCAN_BLK1
U12
PWM1/SCAN_BLK2
T12
LPLL_FBCLK
G3
LPLL_OUTCLK
E17
LPLL_REFIN
H3
AVDD_1
F4
AVDD_2
F5
AVDD_DDR_C_1
F10
AVDD_DDR_C_2
G10
AVDD_DDR_D_1
F11
AVDD_DDR_D_2
F12
AVDD_DDR_D_3
G11
AVDD_DDR_D_4
G12
AVDD_LVDS3.3V_1
D4
AVDD_LVDS3.3V_2
D5
AVDD_LVDS3.3V_3
E4
AVDD_LVDS3.3V_4
E5
AVDD_MPLL3.3V
M5
AVDD_LPLL3.3V
L4
AVDD_PLL3.3V
L5
AVDDL_MOD1.26V
K10
DVDD_DDR_1.26V
L10
DVDD_HF1.26V
K9
VD33_1
M4
VD33_2
N4
VD33_3
N5
VDDC_1.26V_1
M9
VDDC_1.26V_2
M10
VDDC_1.26V_3
N9
VDDC_1.26V_4
N10
VDDC_1.26V_5
N11
VDDC_1.26V_6
P10
VDDC_1.26V_7
P11
RXBCLKP
R2
RXBCLKN
R3
RXB0P
R4
RXB0N
R5
RXB1P
T4
RXB1N
U4
RXB2P
U3
RXB2N
T3
RXB3P
T2
RXB3N
U2
RXB4P
T1
RXB4N
R1
RXACLKP
R6
RXACLKN
R7
RXA0P
R8
RXA0N
R9
RXA1P
T8
RXA1N
U8
RXA2P
U7
RXA2N
T7
RXA3P
T6
RXA3N
U6
RXA4P
U5
RXA4N
T5
XTALO
J1
XTALI
J2
GPIO0/(UART_RX/S_PIF_DA0)
R13
GPIO1
P9
GPIO2/(S_PIF_CLK)
T13
GPIO3/(LTD_DA1)
U15
GPIO4/(LTD_DE)
R14
GPIO5/(LTD_CLK)
K2
GPIO6/(LTD_DA0)
K1
GPIO7(3D_FLAG)
T14
GPIO8
P8
GPIO9/(UART_TX/S_PIF_DA1)
U14
GPIO10/(S_PIF_FC)
U13
GPIO11/(S_PIF_CS)
R12
VSYNC_LIKE
E11
M_S_PIF_CLK
N2
M_S_PIF_CS
M1
M_S_PIF_DA0
N1
M_S_PIF_DA1
N3
M_S_PIF_FC
M3
S_M_PIF_CLK
L1
S_M_PIF_CS
M2
S_M_PIF_DA0
L2
S_M_PIF_DA1
K3
S_M_PIF_FC
L3
SOFT_RST_L
R10
SOFT_RST_R
T11
OP_SYNC_L
R11
OP_SYNC_R
U11
FRC_BA0
33
R9645
SCL2_+3.3V_DB
22uF
10V
C9613
TXDCLKP
FRC_BA2
0 . 1 u F
C9627
0 . 1 u F
C9610
FRC_RASB
TXB0N
TXACLKP
FRC_DQL[0-7]
0 . 1 u F
C9621
TXD3N
TXC1P
33
R9651
URSA_SCL
SDA2_+3.3V_URSA
FRC_VDD33
10K
R9606
DVDD_DDR_1V
4.7K
R9648
0 . 2 2 u F
6.3V
C9629
10K
OPT
R9609
10K
OPT
R9604
33
R9649
1M
R9639
TXB3N
TXB4P
10K
OPT
R9605
+3.3V_FRC
0 . 2 2 u F
6.3V
C9624
10K
OPT
R9607
10K
R9612
0
R9621
OPT
SDA2_+3.3V_DB
FRC_RESET
TXBCLKN
BLM18SG121TN1D
L9604
0
R9619
OPT
10K
OPT
R9617
TXC0P
URSA_MODEL_OPT_1
33
R9647
TXC2P
BLM18SG121TN1D
L9600
URSA_MODEL_OPT_2
+1.5V_FRC_DDR
1uF
6.3V
C9633
TXB1N
22uF
10V
C9608
33
R9646
AFRC_VDD33
0 . 1 u F
C9617
+1.5V_FRC_DDR
PWM1_CONFIG
TXA3N
TXA2P
TXC1N
FRC_BA1
BLM18SG121TN1D
L9602
TXC4N
W25X20BVSNIG
IC9601
URSA5_FLASH_WINBOND_2M
3
WP
2
DO
4
GND
1
CS
5
DIO
6
CLK
7
HOLD
8
VCC
0 . 1 u F
C9601
10K
R9630
22 R9601
URSA5_DEBUG
0 . 1 u F
C9623
33 R9623
SPI_DO
SPI_CS
+3.3V_FRC
TXDCLKN
TXD4P
FRC_VDDC10
TP9605 TP9601 TP9602 TP9603 TP9604 TP9600
1/16W
4.7K
5%
R9643 1/16W
4.7K
5%
R9642
+3.3V_FRC
12505WS-04A00
P9600
URSA5_DEBUG
1
2
3
4
5
24MHz
X9600
4
GND_2
X-TAL_1
2
GND_1
3
X-TAL_2
10pF
C9635
10pF
C9636
RXA4- RXA1+
100
R9632
RXB0-
100
R9624
100
R9625
100
R9629
RXA4+
100
R9626
RXB1+ RXB3-
100
R9633
100
R9628
RXBCK- RXB4+
100
R9634
RXBCK+ RXB0+
100
R9636
RXB3+ RXB1- RXB2- RXA2+ RXA1-
100
R9627
RXB4- RXA0-
100
R9631
100
R9635
RXB2+ RXA2- RXACK+ RXA0+ RXACK- RXA3+ RXA3-
FRC_A[12]
FRC_A[0]
FRC_DQU[1]
FRC_DQU[0]
FRC_DQU[2]
FRC_DQU[6]
FRC_DQL[4]
FRC_A[8]
FRC_A[3]
FRC_DQL[7]
FRC_A[7]
FRC_A[13]
FRC_DQU[5]
FRC_DQL[1]
FRC_DQL[6]
FRC_DQL[2]
FRC_DQL[3]
FRC_DQU[4]
FRC_DQL[0]
FRC_A[10]
FRC_A[2]
FRC_A[1]
FRC_A[11]
FRC_DQU[7]
FRC_DQL[5]
FRC_DQU[3]
FRC_A[9]
FRC_A[5]
FRC_A[6]
FRC_A[4]
URSA5 block
LB3AC
15 13
2 0 1 3 . 0 1 . 2 3
URSA_MODEL_OPT_0
RESERVED
GPIO1 : HI => B8/94, LOW => B4/98
URSA5 H/W OPTION
L/DIM_16BLOCK
P l a c e C l o s e t o B e a d
D11
HIGH
(VDDP)
MODEL OPTION
CHIP_CONF : {GPIO8, PWM1, PWM0}
CHIP_CONF = 3’d5 : boot from interal SRAM
CHIP_CONF = 3’d6 : boot from EEPROM
C H I P _ C O N F = 3 ’ d 7 : b o o t f r o m S P I F l a s h
L/DIM_10BLOCK
RESERVED
LVDS_S7M_PLUS
URSA5 CONFIGURATION
D10
URSA_MODEL_OPT_1
LVDS_EXT_URSA5
PLACE TERMINATION RESISTORS CLOSE TO URSA5
[SPI FLASH(2Mbit)]
PIN NAME
LOW
PIN NO.
URSA_MODEL_OPT_2 D12
Debugging for URSA5
RESERVED RESERVED
D13
URSA_MODEL_OPT_3
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only