LG 55UB820T, Service Manual

Page: 27 / 89

THERMAL
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
M0_DDR_DQ10
M1_DDR_DM1
M0_DDR_DQ30
M0_DDR_DQ14
M0_DDR_VREFDQ
M1_DDR_DQ19
M0_DDR_DQS_N1
M0_DDR_DQS0
M1_DDR_A13
M0_DDR_DQ25
M1_DDR_RESET_N
M0_DDR_DQ28
M0_DDR_DQ29
M0_DDR_DQ4
M0_DDR_DQ4
M0_DDR_ODT
M0_DDR_DQ26
C440 0.1uF
M0_DDR_CKE
M1_DDR_DQ18
M1_DDR_DQ20
M0_DDR_RESET_N
M0_DDR_DQS2
M1_DDR_DQ7
R426
1K
1%
M0_DDR_DQ3
C470
0.1uF
M0_DDR_DQ14
M1_DDR_DQ28
M0_DDR_DQS_N0
M1_DDR_DQ5
M1_DDR_DQ10
M1_DDR_DQ6
M1_DDR_A14
R418
10K
M0_DDR_DQ12
M0_DDR_DQ15
M0_DDR_DQ13
M0_DDR_DQ3
M0_DDR_DM3
M1_DDR_A11
M1_DDR_CKE
M0_1_DDR_VREFDQ
R410
1K
1%
C473
0.1uF
M0_DDR_A11
VDDC15_M0
M0_DDR_DQS1
M0_DDR_DQS3
M0_DDR_A7
M0_DDR_DQS3
M0_DDR_BA0
R405
10K
M1_DDR_DQ11
M1_DDR_A1
M1_DDR_BA2
M0_DDR_A11
M1_DDR_DQ22
M0_D_CLKN
M0_DDR_DQ30
M0_DDR_A15
M0_1_DDR_VREFDQ
R416
1K
1%
M0_DDR_A8
M1_DDR_DQ25
M1_DDR_BA0
M1_DDR_DQ26
M0_DDR_RASN
M1_DDR_A2
M0_DDR_A6
R431
1K
1%
M1_DDR_VREFDQ
VDDC15_M0
M1_DDR_A9
M0_DDR_DQ16
M0_DDR_A12
M1_DDR_A5
M1_DDR_DQ12
M1_DDR_RASN
M0_DDR_DQ15
M0_DDR_DQ6
M1_DDR_A3
M0_DDR_DQ8
M0_DDR_DQ20
M0_D_CLK
M0_DDR_DM2
M0_DDR_DQ27
C411 0.1uF
M0_DDR_DQ22
M0_DDR_A2
M0_DDR_A13
C472
0.1uF
M0_DDR_CASN
R403
240
M1_DDR_DQ0
M0_DDR_DQ25
M1_DDR_DQ29
M0_DDR_VREFDQ
M1_DDR_DQ9
M0_DDR_DM1
M0_DDR_DQ0
M1_DDR_A7
M0_DDR_DQ21
M0_DDR_A4
M1_DDR_DQ13
M0_DDR_CASN
C410 0.1uF
M1_DDR_DQ16
M0_DDR_DQ5
M1_DDR_DM2
M0_DDR_DM0
M1_DDR_A0
M0_DDR_DQ10
M0_DDR_A5
M0_DDR_DM0
M0_DDR_DQ18
M0_DDR_DQS_N0
M1_D_CLKN
VDDC15_M0
M0_DDR_DQ7
C479
0.1uF
M0_DDR_DQ2
VDDC15_M0
M0_DDR_A10
M1_DDR_DQ14
M1_DDR_RESET_N
M0_DDR_DQ29
M0_DDR_DQS1
M0_DDR_DQ17
M1_DDR_DQ1
M0_DDR_RESET_N
M0_DDR_BA1
M0_DDR_DQS_N2
M1_DDR_DQ23
VDDC15_M0
R425
1K
1%
M1_DDR_CASN
M0_DDR_DQ8
M0_DDR_BA1
M0_DDR_DM2
M1_DDR_DQS_N2
M0_DDR_DQ1
M1_DDR_WEN
M1_DDR_A4
M0_DDR_DQ5
M0_DDR_A9
M0_DDR_DM1
M0_DDR_A1
R417
1K
1%
M1_DDR_DQ24
M0_DDR_DQ18
M1_DDR_DQ31
M1_DDR_DQ21
M0_DDR_CKE
M0_DDR_DQ31
M0_DDR_A15
M0_DDR_DQ13
M0_DDR_DQ19
M0_D_CLK
M0_DDR_A3
M1_DDR_DQS_N1
M1_DDR_ODT
M1_DDR_DQS2
M1_DDR_DQ4
M0_DDR_A2
M0_DDR_DQ12
M1_DDR_A8
R422
10K
M0_DDR_DQ11
M0_DDR_DQ6
M0_DDR_A6
M1_DDR_DQ27
M0_DDR_BA0
M0_DDR_DQ7
M1_DDR_DQ15
M0_DDR_DQ26
M0_DDR_A0
M0_DDR_A1
VDDC15_M0
M0_DDR_A0
M0_DDR_DQ22
M0_DDR_WEN
VDDC15_M0
M1_DDR_DQ17
M1_DDR_DM3
M1_DDR_DQS3
M1_DDR_DQ30
M1_D_CLK
M0_DDR_A10
M1_DDR_CKE
M1_DDR_DQS_N3
M0_DDR_DQ24
M1_DDR_DQ2
M0_DDR_CKE
M0_DDR_RESET_N
M1_DDR_A15
M0_DDR_ODT
M0_DDR_DQ19
R411
1K
1%
M0_DDR_DQS0
M0_DDR_DQS_N3
M0_DDR_DQ1
M1_DDR_A12
M0_DDR_DQS_N2
M0_DDR_A9
M0_DDR_A13
M1_DDR_DM0
M1_DDR_BA1
M0_DDR_DQ9
M0_DDR_A5
C441 0.1uF
M0_DDR_DQ2
M1_DDR_DQ3
M0_DDR_DQ11
M0_D_CLKN
M0_DDR_DQ0
M0_DDR_BA2
M0_DDR_DQ23
M0_DDR_DQ27
M1_DDR_DQ8
M1_DDR_DQS1
M1_DDR_A10
M0_DDR_DQ24
M0_DDR_A14
M0_DDR_A3
M0_DDR_DQS_N3
M0_DDR_DM3
M1_DDR_A6
M0_DDR_DQ28
R433
10K
M0_DDR_DQ23
M0_DDR_DQ21
M0_DDR_DQ9
M1_DDR_DQS0
M0_DDR_DQS_N1
M0_DDR_DQ20
M0_DDR_DQ16
M1_1_DDR_VREFDQ
M0_DDR_DQ31
R400 240
M0_DDR_A8
M0_DDR_A7
VDDC15_M0
M0_DDR_DQS2
M1_DDR_DQS_N0
M0_DDR_WEN
M0_DDR_A12
M0_DDR_A14
M0_DDR_RASN
M0_DDR_DQ17
R432
1K
1%
M0_DDR_A4
M0_DDR_BA2
M1_DDR_DM3
M1_D_CLK
M1_DDR_A3
M1_DDR_DQ24
C490 0.1uF
M1_DDR_DQ7
M1_DDR_BA2
M1_DDR_DQS0
M1_DDR_A15
M1_DDR_A6
M1_DDR_A5
M1_DDR_A9
M1_DDR_CASN
M1_DDR_DQ31
M1_DDR_CASN
M1_DDR_DQ3
M1_DDR_DM2
M1_DDR_DQ17
M1_DDR_DQ11
M1_DDR_CKE
M1_1_DDR_VREFDQ
M1_D_CLK
M1_DDR_A5
M1_DDR_A12
M1_DDR_DQ26
M1_DDR_DQ6
M1_DDR_A14
M1_DDR_A6
M1_DDR_DQ23
M1_DDR_DQ9
M1_DDR_RASN
C468 0.1uF
M1_DDR_DM1
R404
240
R419
240
M1_DDR_A0
M1_DDR_DQ14
M1_DDR_DQ2
M1_DDR_ODT
M1_DDR_A8
M1_DDR_DQ18
M1_DDR_A1
M1_DDR_DQS1
M1_DDR_BA0
M1_DDR_DQ27
M1_DDR_DQ28
C491 0.1uF
M1_DDR_WEN
M1_DDR_DQ21
M1_DDR_DQ1
M1_DDR_DQS3
M1_DDR_A1
M1_DDR_A4
M1_DDR_DQS_N0
M1_DDR_A10
M1_DDR_DQS_N3
M1_DDR_RASN
M1_DDR_DQ12
M1_DDR_A10
M1_DDR_DQ29
M1_DDR_DQ30
M1_DDR_A11
M1_DDR_CKE
M1_DDR_BA1
M1_DDR_A13
M1_DDR_RESET_N
C469 0.1uF
M1_DDR_A8
M1_DDR_DQ8
M1_DDR_A2
M1_DDR_DQ22
M1_DDR_DQ4
M1_DDR_DQ16
M1_DDR_A4
M1_DDR_DM0
M1_DDR_A7
M1_DDR_DQ25
M1_DDR_BA2
M1_DDR_DQ20
M1_DDR_BA1
M1_DDR_DQ15
M1_DDR_A12
M1_DDR_A7
M1_DDR_A9
M1_DDR_DQS2
VDDC15_M0
M1_DDR_ODT
M1_DDR_DQS_N2
M1_DDR_BA0
M1_DDR_RESET_N
M1_DDR_DQ13
M1_DDR_A3
M1_D_CLKN
M1_DDR_A0
M1_DDR_VREFDQ
M1_DDR_DQ19
M1_DDR_A13
M1_D_CLKN
M1_DDR_A15
M1_DDR_A2
VDDC15_M0
M1_DDR_A14
M1_DDR_DQ0
M1_DDR_DQS_N1
M1_DDR_A11
M1_DDR_DQ10
M1_DDR_WEN
M1_DDR_DQ5
M0_DDR_A12
M0_DDR_CKE
M0_DDR_BA1
M0_DDR_A2
M0_DDR_A8
M0_DDR_A13
M0_DDR_A4
M0_DDR_BA2
M0_DDR_A0
M0_DDR_BA0
M0_D_CLK
M0_DDR_RASN
M0_DDR_CASN
M0_DDR_A15
M0_DDR_RESET_N
M0_DDR_A3
M0_DDR_A14
M0_DDR_A11
M0_DDR_A6
M0_DDR_A1
M0_DDR_A10
M0_DDR_A9
M0_DDR_WEN
M0_DDR_A7
M0_DDR_A5
M0_D_CLKN
M0_DDR_ODT
M0_DDR_CS1
M0_DDR_CS2
M1_DDR_CS1
M1_DDR_CS2
M0_DDR_CS1
M0_DDR_CS2
M1_DDR_CS1
M1_DDR_CS2
C474
1000pF
50V
C483
1000pF
50V
C471
1000pF
50V
C478
1000pF
50V
C407
0.1uF
C409
0.1uF
C405
0.1uF
C408
0.1uF
C402
0.1uF
C400
0.1uF
C406
0.1uF
C403
0.1uF
C401
0.1uF
C404
0.1uF
VDDC15_M0
C412
0.1uF
C420
0.1uF
VDDC15_M0
C416
0.1uF
C418
0.1uF
C438
0.1uF
C439
0.1uF
C423
0.1uF
C419
0.1uF
C413
0.1uF
C415
0.1uF
C444
0.1uF
C450
0.1uF
VDDC15_M0
C447
0.1uF
C448
0.1uF
C452
0.1uF
C467
0.1uF
C451
0.1uF
C449
0.1uF
C445
0.1uF
C446
0.1uF
C475
0.1uF
C486
0.1uF
VDDC15_M0
C481
0.1uF
C484
0.1uF
C488
0.1uF
C489
0.1uF
C487
0.1uF
C485
0.1uF
C476
0.1uF
C480
0.1uF
R412
56
1%
C477
0.01uF
50V
M0_D_CLKN
R413
56
1%
M0_D_CLK
R427
56
1%
M1_D_CLK
C497
0.01uF
50V
M1_D_CLKN
R428
56
1%
C421
1000pF
VDDC15_M0
R402
10K
1%
C417
100uF
C422
22uF
10V
+3.3V_NORMAL
IC402
TPS51200DRCR
3
VO
2
VLDOIN
4
PGND
1
REFIN
5
VOSNS
6
REFOUT
7
EN
8
GND
9
PGOOD
10
VIN
11
[EP]
C414
0.1uF
C443
4700pF
L401
UBW2012-121F
C442
0.1uF
L400
UBW2012-121F
DDR_VTT
R401
10K 1%
M0_DDR_CASN
M0_DDR_A14
M0_DDR_A10
M0_DDR_A15
M0_DDR_ODT
M0_DDR_BA0
M0_DDR_WEN
M0_DDR_A11
M0_DDR_BA2
M0_DDR_A4
M0_DDR_A3
M0_DDR_A0
M0_DDR_A7
M0_DDR_A8
M0_DDR_A13
M0_DDR_CKE
M0_DDR_BA1
M0_DDR_A6
M0_DDR_A1
M0_DDR_A5
M0_DDR_RASN
M0_DDR_A9
M0_DDR_A12
M0_DDR_A2
M0_D_CLKN
M0_D_CLK
M1_DDR_CASN
M1_DDR_A5
M1_DDR_A10
M1_DDR_A4
M1_DDR_A6
M1_DDR_BA0
M1_DDR_A9
M1_DDR_BA1
M1_DDR_A8
M1_DDR_CKE
M1_DDR_A2
M1_DDR_WEN
M1_DDR_A0
M1_DDR_RASN
M1_DDR_A7
M1_DDR_BA2
M1_D_CLK
M1_DDR_A13
M1_DDR_A14
M1_DDR_A3
M1_DDR_ODT
M1_DDR_A12
M1_DDR_A11
M1_DDR_A1
M1_D_CLKN
M1_DDR_A15
AR400
100
1/16W
AR401
100
1/16W
AR403
100
1/16W
AR402
100
1/16W
AR405
100
1/16W
AR404
100
1/16W
AR406
100
1/16W
AR412
100
1/16W
AR413
100
1/16W
AR411
100
1/16W
AR408
100
1/16W
AR407
100
1/16W
AR410
100
1/16W
AR409
100
1/16W
DDR_VTT
C424 0.1uF
C425 0.1uF
C426 0.1uF
C427 0.1uF
C428 0.1uF
C429 0.1uF
C430 0.1uF
C431 0.1uF
C432 0.1uF
C433 0.1uF
C434 0.1uF
C435 0.1uF
C436 0.1uF
C437 0.1uF
C462 0.1uF
C456 0.1uF
C453 0.1uF
C461 0.1uF
C466 0.1uF
C455 0.1uF
C460 0.1uF
C465 0.1uF
DDR_VTT
C459 0.1uF
C464 0.1uF
C458 0.1uF
C463 0.1uF
C454 0.1uF
C457 0.1uF
M0_DDR_RESET_N M1_DDR_RESET_N
IC100
LGE4331
A_DDR3_A0
F16
A_DDR3_A1
C16
A_DDR3_A2
E16
A_DDR3_A3
F17
A_DDR3_A4
B17
A_DDR3_A5
E17
A_DDR3_A6
A16
A_DDR3_A7
D16
A_DDR3_A8
C15
A_DDR3_A9
E15
A_DDR3_A10
B18
A_DDR3_A11
B16
A_DDR3_A12
D19
A_DDR3_A13
F15
A_DDR3_A14
B15
A_DDR3_A15
E19
A_DDR3_BA0
E18
A_DDR3_BA1
C17
A_DDR3_BA2
F18
A_DDR3_RASZ
F20
A_DDR3_CASZ
F19
A_DDR3_WEZ
E20
A_DDR3_ODT
G21
A_DDR3_CKE
C18
A_DDR3_RST
F14
A_DDR3_MCLK
A19
A_DDR3_MCLKZ
B19
A_DDR3_CSB1
E14
A_DDR3_CSB2
D14
A_DDR3_DQ[0]
C22
A_DDR3_DQ[1]
B21
A_DDR3_DQ[2]
B23
A_DDR3_DQ[3]
C20
A_DDR3_DQ[4]
B24
A_DDR3_DQ[5]
C19
A_DDR3_DQ[6]
C23
A_DDR3_DQ[7]
C21
A_DDR3_DQM[0]
B20
A_DDR3_DQS[0]
A22
A_DDR3_DQSB[0]
B22
A_DDR3_DQ[8]
F22
A_DDR3_DQ[9]
E24
A_DDR3_DQ[10]
E21
A_DDR3_DQ[11]
E25
A_DDR3_DQ[12]
D22
A_DDR3_DQ[13]
D26
A_DDR3_DQ[14]
D21
A_DDR3_DQ[15]
D25
A_DDR3_DQM[1]
E23
A_DDR3_DQS[1]
D23
A_DDR3_DQSB[1]
E22
A_DDR3_DQ[16]
C27
A_DDR3_DQ[17]
C25
A_DDR3_DQ[18]
B28
A_DDR3_DQ[19]
A25
A_DDR3_DQ[20]
C28
A_DDR3_DQ[21]
C24
A_DDR3_DQ[22]
A28
A_DDR3_DQ[23]
B26
A_DDR3_DQM[2]
B25
A_DDR3_DQS[2]
B27
A_DDR3_DQSB[2]
C26
A_DDR3_DQ[24]
D28
A_DDR3_DQ[25]
C29
A_DDR3_DQ[26]
E26
A_DDR3_DQ[27]
D29
A_DDR3_DQ[28]
E28
A_DDR3_DQ[29]
D30
A_DDR3_DQ[30]
E27
A_DDR3_DQ[31]
C30
A_DDR3_DQM[3]
B30
A_DDR3_DQS[3]
A30
A_DDR3_DQSB[3]
B29
B_DDR3_A0
G28
B_DDR3_A1
J31
B_DDR3_A2
H29
B_DDR3_A3
J27
B_DDR3_A4
J30
B_DDR3_A5
H28
B_DDR3_A6
J32
B_DDR3_A7
G31
B_DDR3_A8
H32
B_DDR3_A9
F30
B_DDR3_A10
K30
B_DDR3_A11
H30
B_DDR3_A12
K29
B_DDR3_A13
F31
B_DDR3_A14
H31
B_DDR3_A15
L28
B_DDR3_BA0
K28
B_DDR3_BA1
K31
B_DDR3_BA2
J28
B_DDR3_RASZ
M27
B_DDR3_CASZ
L27
B_DDR3_WEZ
K27
B_DDR3_ODT
M28
B_DDR3_CKE
L31
B_DDR3_RST
F32
B_DDR3_MCLK
M32
B_DDR3_MCLKZ
L30
B_DDR3_CSB1
F29
B_DDR3_CSB2
E32
B_DDR3_DQ[0]
R31
B_DDR3_DQ[1]
N30
B_DDR3_DQ[2]
R30
B_DDR3_DQ[3]
N31
B_DDR3_DQ[4]
T30
B_DDR3_DQ[5]
M31
B_DDR3_DQ[6]
T31
B_DDR3_DQ[7]
P31
B_DDR3_DQM[0]
M30
B_DDR3_DQS[0]
R32
B_DDR3_DQSB[0]
P30
B_DDR3_DQ[8]
P28
B_DDR3_DQ[9]
T28
B_DDR3_DQ[10]
N28
B_DDR3_DQ[11]
U28
B_DDR3_DQ[12]
N27
B_DDR3_DQ[13]
T27
B_DDR3_DQ[14]
N29
B_DDR3_DQ[15]
T29
B_DDR3_DQM[1]
R28
B_DDR3_DQS[1]
R27
B_DDR3_DQSB[1]
P27
B_DDR3_DQ[16]
Y31
B_DDR3_DQ[17]
V31
B_DDR3_DQ[18]
Y30
B_DDR3_DQ[19]
V32
B_DDR3_DQ[20]
AA30
B_DDR3_DQ[21]
U31
B_DDR3_DQ[22]
AA31
B_DDR3_DQ[23]
V30
B_DDR3_DQM[2]
U30
B_DDR3_DQS[2]
W30
B_DDR3_DQSB[2]
W31
B_DDR3_DQ[24]
V28
B_DDR3_DQ[25]
Y27
B_DDR3_DQ[26]
U27
B_DDR3_DQ[27]
AA28
B_DDR3_DQ[28]
W28
B_DDR3_DQ[29]
AA29
B_DDR3_DQ[30]
V27
B_DDR3_DQ[31]
AA27
B_DDR3_DQM[3]
W27
B_DDR3_DQS[3]
Y28
B_DDR3_DQSB[3]
W29
H5TQ4G63AFR-RDC
IC400
EAN63053201
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
H5TQ4G63AFR-RDC
IC401
EAN63053201
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
H5TQ4G63AFR-RDC
IC403
EAN63053201
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
H5TQ4G63AFR-RDC
IC404
EAN63053201
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
C4000
10uF
10V
OPT
C4001
10uF
10V
OPT
C4002
10uF
10V
OPT
C4003
10uF
10V
OPT
C4004
1uF
25V
OPT
C4005
1uF
25V
OPT
C4006
1uF
25V
OPT
C4007
1uF
25V
OPT
C4008
0.1uF
16V
OPT
C4009
0.1uF
16V
OPT
C4010
0.1uF
16V
OPT
C4011
0.1uF
16V
OPT
DDR3 1.5V bypass Cap - Place these caps near Memory DDR3 1.5V bypass Cap - Place these caps near Memory
DDR3
4Gbit
(x16)
DDR3
4Gbit
(x16)
DDR3 1.5V bypass Cap - Place these caps near Memory DDR3 1.5V bypass Cap - Place these caps near Memory
DDR3
4Gbit
(x16)
DDR3
4Gbit
(x16)
2013-10-28
LM14 DDR
UB83
04
+1.5V_Bypass Cap
Close to DDR Power Pin
+1.5V_Bypass Cap
Close to DDR Power Pin
+1.5V_Bypass Cap
Close to DDR Power Pin
+1.5V_Bypass Cap
Close to DDR Power Pin
* DDR_VTT
Close to REFOUT pin
4th layer
4th layer
4th layer
4th layer
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Only for training and service purposes LGE Internal Use Only