THERMAL
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
+1.8V_DDR
TU_SCL
RXB4+
+3.3V_ST
P_AMP_SCL
IR
AUD_LRCK
D2-_HDMI1
+3.3V_ST
+3.3V_ST
RXA3+
MODEL_OPT1
DDR_DATA
DDR_CMD
RXBCK-
RXACK+
AVDD_DADC
SOC_RESET
RXB1+
RXA0-
SIDE_USB_DP
/SPI_CS
DDC_SDA_1
+3.3V_ST
+3.3V
MODULE_UART_RXD
USB1_CTL
+3.3V
D1-_HDMI1
RXBCK+
KEY1
AUD_SCK
SPI_SDI
KEY2
SOC_RESET
+1.15V_VDDC
RXA2-
+3.3V
CK+_HDMI1
RXA4-
RL_ON
VS_ON
DDC_SCL_1
RXB0-
AVDD_MOD
D0+_HDMI1
D2+_HDMI1
AC_DET
HPD1
TU_SDA
AVDD_DMPLL
+1.8V_DDR
AVDD_AU33
AVDD_MOD
USB1_OCD
P_AMP_SDA
+1.15V_VDDC
AVDD_MOD
/FLASH_WP
5V_DET_HDMI_1
DDR_CMD
I2C_SCL
AVDD_MOD
+1.15V_VDDC
P_AMP_SCL
RXB2-
COMP_L_IN
RXA2+
IF_AGC_MAIN
IF_P_MSTAR
+1.15V_VDDC
AVDD_DMPLL
RXB1-
I2C_SDA
AV_DET
+3.3V_ST
MODULE_UART_TXD
RXA1+
+3.3V_ST
RXB3+
RXA1-
SPDIF_OUT
DISP_EN
RXB2+
RXA4+
+1.15V_VDDC
AVDD_AU33
AUD_MASTER_CLK
P_AMP_SDA
SPI_SCK
AVDD_MOD
CK-_HDMI1
I2C_SCL
RXACK-
RXB4-
RXA0+
D0-_HDMI1
RXA3-
RXB0+
AVDD_DADC
SIDE_USB_DM
COMP_R_IN
I2C_SDA
AVDD_VIDEO
D1+_HDMI1
MODEL_OPT1
17V_VS_DET
CEC
IF_N_MSTAR
SPI_SDO
RXB3-
DDR_DATA
DISP_EN
5V_ON
AUD_LRCH
AVDD_VIDEO
LED_RED
AMP_MUTE
MODULE_UART_TXD
MODULE_UART_RXD
PM_RXD
PM_TXD
EYE_SCL
EYE_SDA
AMP_RESET_N
PWM1
PWM0
PWM0
PWM1
MODEL_OPT2
MODEL_OPT2
COMP_DET
L410
BLM18PG121SN1D
X400
24MHz
4
GND_2
1
X-TAL_1
2 GND_1
3
X-TAL_2
R403
100K
C429
0.047uF
C442
0.1uF
C468
0.1uF
R443
33
R446
33
R411
1K
C440
0.1uF
C441
0.1uF
C497
10uF
10V
R445
68
L400
C464
100pF
READY
C406
2.2uF
C449
0.047uF
L406
C433
0.047uF
C405
2.2uF
C478
0.1uF
C462
0.1uF
C407
0.1uF
C409
0.1uF
C439
0.047uF
R414
33
C410
0.1uF
R471
100
C408
0.1uF
L401
R434
33
C411
0.1uF
C480
0.1uF
C443
1000pF
C469
0.047uF
25V
C438
0.1uF
TP4
C445
0.1uF
L403
R444
33
L402
R410
1K
HD
C402
0.1uF
R413
33
C461
0.1uF
C452
10pF
L405
R409
1K
FHD
C474
0.1uF
C451
10pF
R447
1M
C430
0.047uF
C463
100pF
READY
10uF
C455
10uF
C434
C482
0.1uF
D400
C401
0.1uF
L404
C413
0.047uF
R469
10K
R408
22
L408
BLM18PG121SN1D
R426
150
R427
180
R407
33
TP5
R401
33
R421
100
R450
4.7K
R453
4.7K
R452
4.7K
R474
4.7K
R451
4.7K
R464
4.7K
R465
0
R466
0
R415
100
R416
100
R417
100
C467
1uF
R402
1K
IC400
LGE8220(MSD8220LBM)
1
RX1N_B
2
RX1P_B
3
RX2N_B
4
RX2P_B
5
AVDD_MOD_1
6
RXCN_A
7
RXCP_A
8
RX0N_A
9
RX0P_A
10
RX1N_A
11
RX1P_A
12
RX2N_A
13
RX2P_A
14
HSYNC0
15
BIN0P
16
SOGIN0
17
GIN0P
18
GIN0M
19
RIN0P
20
VSYNC0
21
AVDD3P3_ADC
22
BIN1P
23
SOGIN1
24
GIN1P
25
GIN1M
26
RIN1P
27
VSYNC1
28
CVBS1
29
CVBS0
30
VCOM
31
CVBS_OUT1
32
VDDC_1
33
AVDD_AU33
34
AUR0
35
AUL0
36
AUR1
37
AUL1
38
AUR2
39
AUL2
40
AUR3
41
AUL3
42
VAG
43
VRM
44
LINEOUTL3
45
LINEOUTR3
46
LINEOUTL0
47
LINEOUTR0
48
IFAGC
49
VIFP
50
VIFM
51
AVDD3P3_DADC
52
AVDD3P3_DMPLL
53
XIN
54
XOUT
55
AVDD_MOD_2
56
VDDIO_CMD
57
VDDC_2
58
GPIO44/I2C_SDAM/UART_TX1
59
GPIO45/I2C_SCLM/UART_RX1
60
GPIO46/MHL_VBUS
61
GPIO47
62
GPIO49/SPDIF_OUT
63
GPIO50/I2S_OUT_WS
64
GPIO51/I2S_OUT_MCK
65
GPIO52/I2S_OUT_BCK
66
GPIO53/I2S_OUT_SD
67
B_ODD[0]/LVA4+/LLV6+
68
B_ODD[1]/LVA4-/LLV6-
69
B_ODD[2]/LVA3+/LLV5+
70
B_ODD[3]/LVA3-/LLV5-
71
B_ODD[4]//LLV4+
72
B_ODD[5]/LVACLK-/LLV4-
73
B_ODD[6]/LVA2+/LLV3(CLK)+
74
B_ODD[7]/LVA2-/LLV3(CLK)-
75
G_ODD[0]/LVA1+/LLV2+/EPI0+
76
G_ODD[1]/LVA1-/LLV2-/EPI0-
77
G_ODD[2]/LVA0+/LLV1+/EPI1+
78
G_ODD[3]/LVA0-/LLV1-/EPI1-
79
G_ODD[4]/LVB4+/LLV0+/EPI2+
80
G_ODD[5]/LVB4-/LLV0-/EPI2-
81
G_ODD[6]/LVB3+/RLV6+/EPI3+
82
G_ODD[7]/LVB3-/RLV6-/EPI3-
83
R_ODD[0]//RLV5+/EPI4+
84
R_ODD[1]/LVBCLK-/RLV5-/EPI4-
85
R_ODD[2]/LVB2+/RLV4+/EPI5+
86
R_ODD[3]/LVB2-/RLV4-/EPI5-
87
AVDD_MOD_3
88
R_ODD[4]/LVB1+/RLV3(CLK)+/EPI6+
89
R_ODD[5]/LVB1-/RLV3(CLK)-/EPI6-
90
R_ODD[6]/LVB0+/RLV2+/EPI7+
91
R_ODD[7]/LVB0-/RLV2-/EPI7-
92
LCK/GPIO19/RLV1+/GPIO19
93
LDE/GPIO18/RLV1-/GPIO18
94
LHSYNC/GPIO17/RLV0+/GPIO17
95
LVSYNC/GPIO16/RLV0-/GPIO16
96
GPIO10/TCON10
97
GPIO9/TCON9
98
GPIO8/TCON8
99
GPIO7/TCON7
100
GPIO6/TCON6
101
GPIO5/TCON5
102
GPIO4/TCON4
103
GPIO3/TCON3
104
GPIO2/TCON2
105
GPIO1/TCON1
106
GPIO0/TCON0
107
HOTPLUG_D
108
HOTPLUG_A
109
PWM1/GPIO14
110
PWM0/GPIO15
111
SPI_DO
112
SPI_DI
113
SPI_CZ
114
SPI_CK
115
ARC/GPIO87
116
DDCA_DA
117
DDCA_CK
118
TEST
119
CEC
120
IRIN
121
INT/GPIO64/I2S_OUT_MCK
122
RESET
123
DM_P0
124
DP_P0
125
DM_P1
126
DP_P1
127
AVDD_MOD_4
128
SAR0/GPIO75
129
SAR1/GPIO74
130
SAR2/GPIO73
131
VDDC_3
132
VDDIO_DATA
133
GPIO54
134
DDCDD_CL
135
DDCDD_DA
136
DDCDA_CL
137
DDCDA_DA
138
MHL_DET/GPIO86
139
DDCDB_DA
140
DDCDB_CL
141
HOTPLUG_B
142
AVDD_5V_MHL
143
GND_EFUSE
144
VDDC_4
145
RXCN_D
146
RXCP_D
147
RX0N_D
148
RX0P_D
149
RX1N_D
150
RX1P_D
151
RX2N_D
152
RX2P_D
153
RXCN_B
154
RXCP_B
155
RX0N_B
156
RX0P_B
157
E-PAD
1uF
C435
C412
10uF
R459
1K
R461
1K
C436
10uF
C414
10uF
C403
10uF
C404
10uF
CVBS_OUT_TEST
4
L13
MAIN
2012-06-201
7
<SOC_RESET>
MODEL OPTION
<VDDC 1.15V>
HD
PIN NAME
FHD
LOW
<SY-BY Power 3.3V>
HIGH
<DDR 1.8V>
MODEL_OPT_1
DTV_IF
Close to MSTAR
Close to MSTAR
NON_A_DEMODE
AGC 1.25V
100 OHM SERIAL
A_DEMODE 0ohm
<HW_OPT>
[M1L]
Don’t use arc/gpio87 as GPIO
Chip config
MODEL_OPT_2
LCD(NOT USE)
PDP
Copyright
©
2013 LG Electronics Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Summary of Contents for 50PB560B
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