LG 49UF6700, Service Manual

Page: 53 / 57

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
URSA_BIT1
FRC_FLASH_WP
R13241 33
OPT
R13243 33
OPT
URSA_LOCK_O
SDA2_+3.3V_DB
URSA_LOCK_V
Data_Format_1
R13228
10K
SPI_DI
+3.3V_U_NORMAL
URSA_OPT_1
R13206
10K OPT
URSA_SDA
R13212
10K
URSA_BIT0_1
SPI_CZ
URSA_SCL
R13223 33
OPT
R13225
33
OPT
DIM1
R13240
0
OPT
R13237
0
NON_URSA_SLIDE_SW(MP)
+3.3V_U_NORMAL
+3.3V_U_NORMAL
R13220 1M
P13201
12507WS-04L
WAFER-STRAIGHT
URSA_DEBUG
1
2
3
4
5
DIM0
XIN_URSA
URSA9_CONNECT
AR13200
33
D13201 100V 1N4148W
OPT
SPI_CK
SW13002
JS2235S
URSA_SLIDE_SW(DEBUG)
3
2
1
4
5
6
R13208
10K
DIM1
FLASH_WP_URSA
+3.3V_U_NORMAL
R13203
10K
R13234
10K
URSA_RESET
FLASH_WP_URSA
R13244 10K
URSA_RX_Vx1_HTPDn
Data_Format_0
URSA_LOCK_O
SPI_CZ
SDA2_+3.3V_URSA
R13211
10K
OS_Module
R13227 10K
URSA_RX_Vx1_HTPDn
SDA2_+3.3V_DB
R13224 33
OPT
R13226
10K
OPT
SCL2_+3.3V_DB
L_DIM_EN
URSA_LOCK_V
R13235
0
NON_URSA_SLIDE_SW(MP)
URSA_RESET
URSA_OPT_0
R13213
10K
OPT
R13450 10K
R13231
1K
OPT
SPI_DO
R13205 1K
OPT
R13216 33
URSA_DEBUG
R13207
10K OPT
R13217 33
URSA_DEBUG
URSA_BIT2
SPI_CK
SDA2_+3.3V_URSA
URSA_BIT1
TCON_I2C_EN
SCL2_+3.3V_URSA
DIM2
URSA_BIT0
R13245
10K
OPT
R13246 33
DIM2
SPI_DI
R13247
10K
URSA_BIT0_0
URSA_OPT_1
XIN_URSA
R13222 1K
SCL2_+3.3V_URSA
DIM0
URSA_BIT2
R13233
10K
OPT
R13248
10K OPT
R13249
10K
URSA9_CONNECT
R13209
10K
OPT
R13210
10K
LGD_Module
R13214
10K
URSA_RESET_SoC X13201
24MHz
4
GND_2
1
X-TAL_1
2
GND_1
3
X-TAL_2
+3.3V_U_NORMAL
R13201
10K
+3.3V_U_NORMAL
C13235
0.1uF
16V
+3.3V_U_NORMAL
XO_URSA
R13239 33
OPT
R13238
0
OPT
SCL2_+3.3V_DB
XO_URSA
3D_EN
URSA_BIT0
URSA_OPT_0
R13202
10K
SPI_DO
R13232
10K
OPT
R13221
0
IC2500
LGE7411(URSA9)
RESET
AF29
XTALO
R3
XTALI
R4
I2CS_SDA
AJ24
I2CS_SCL
AH24
I2CM_SDA
AH26
I2CM_SCL/VSYNC_LIKE1
AG24
GPIO[0][UART2_TX]
B4
GPIO[1][UART2_RX]
A4
GPIO[2][UART1_TX]
B5
GPIO[3][UART1_RX]
A5
SPI_CZ
AD28
SPI_CK
AD30
SPI_DI
AC31
SPI_DO
AD29
INT_R21/GPIO[41]
AE28
INT_R20/GPIO[42]
AE27
IRE
C4
GND_1
AC27
GND_2
AD27
NC_1
A7
NC_2
B6
NC_3
B7
NC_4
C5
NC_5
C6
NC_6
C7
NC_7
D4
NC_8
D5
NC_9
D6
NC_10
D7
NC_11
E4
NC_12
E5
NC_13
E6
NC_14
E7
NC_15
F4
NC_16
F5
NC_17
M5
NC_18
M6
NC_19
M7
NC_20
N5
NC_21
R7
NC_22
P7
NC_23
N7
NC_24
N6
I2C_HSC_SDA/VSYNC_LIKE2
AG25
I2C_HSC_SCL/VSYNC_LIKE3
AH25
SPI1_CK/PWM2/GPIO58
AH28
SPI1_DI/PWM3/GPIO59
AJ27
SPI2_CK/PWM0/GPIO56
AJ29
SPI2_DI/PWM1/GPIO57
AF27
SPI3_CK/DIM10/GPIO54
AG28
SPI3_DI/DIM11/GPIO55
AH27
SPI4_CK/DIM8/GPIO52
AG27
SPI4_DI/DIM9/GPIO53
AG26
VSYNC_LIKE/PWM5/GPIO40
AF28
DIM0/GPIO[32]
AG23
DIM1/GPIO[33]
AG20
DIM2/GPIO[34]
AH23
DIM3/GPIO[35]
AH20
DIM4/GPIO[36]
AG21
DIM5/GPIO[37]
AH22
DIM6/GPIO[38]
AG22
DIM7/GPIO[39]
AH21
GPIO43/TCON0
A3
GPIO44/TCON1
B3
GPIO45/TCON2
A2
GPIO46/TCON3
C3
GPIO47/TCON4
B2
GPIO48/TCON5
B1
GPIO49/TCON6
C2
GPIO50/TCON7
C1
GPIO[18]/TCON8
AG4
GPIO[19]/TCON9
AG5
GPIO[20]/TCON10
AH4
GPIO[21]/TCON11
AH5
GPIO[22]/TCON12
AH6
GPIO[23]/TCON13
AJ4
GPIO24/TCON14
AJ5
GPIO25/TCON15
AJ6
GPIO[4]
AH16
GPIO[5]
AG16
GPIO[6]
Y5
GPIO[7]
Y4
GPIO[8]
AB4
GPIO[9]
AB5
GPIO[10]/PWM_DIM_IN[0]
AG17
GPIO[11]/PWM_DIM_IN[1]
AH17
GPIO[12]
AG18
GPIO[13]
AJ20
GPIO[14]
AH18
GPIO[15]
AG19
GPIO[16]
AH19
GPIO[17]
AJ21
+3.3V_U_NORMAL
R13215
10K
Div_BIT1
Div_BIT0
URSA_OPT_4
URSA_OPT_5
URSA_OPT_6
R13451
10K
Div_BIT1_1
R13452
10K
Div_BIT1_0
R13453
10K
Div_BIT0_1
R13454
10K
Div_BIT0_0
R13455
10K
Release
R13456
10K
Debug
R13457
10K
OPT
R13458
10K
R13459
10K
OPT
R13460
10K
URSA_OPT_4
Div_BIT0
Div_BIT1
URSA_OPT_6
URSA_OPT_5
R13253 10K
URSA9_SYS_DEBUG
C13239
0.1uF
16V
URSA9_SYS_DEBUG
R13250 10K
URSA9_PQ_DEBUG
R13255
33
URSA9_SYS_DEBUG
R13254
33
URSA9_SYS_DEBUG
+3.3V_U_NORMAL
R13252
33
URSA9_PQ_DEBUG
C13240
0.1uF
16V
URSA9_PQ_DEBUG
R13251
33
URSA9_PQ_DEBUG
+3.3V_U_NORMAL
P13203
12507WS-04L
URSA9_SYS_DEBUG
1
2
3
4
5
P13202
12507WS-04L
URSA9_PQ_DEBUG
1
2
3
4
5
DDC_SCL_2
DDC_SDA_2
HPD2
DDC_SDA_4
DDC_SCL_4
DDC_SCL_2
DDC_SDA_2
HPD2
DDC_SCL_4
DDC_SDA_4
R13218
470K
OPT
C13238
1uF
10V
OPT
P13204
12507WS-04L
OPT
1
2
3
4
5
URSA_L/D_VSYNC
URSA_L/D_VSYNC
R13461 33
OPT
R13462 33
OPT
URSA_OPT_6
URSA_OPT_5
R13230 33
OPT
IC13201-*1
W25Q32FVSSIG
URSA_FLASH_WINDBOND(MULTI)
3
WP[IO2]
2
DO[IO1]
4
GND
1
CS
5
DI[IO0]
6
CLK
7
HOLD_OR_RESET[IO3]
8
VCC
C13236 8pF 50V
C13237 8pF 50V
IC13201
MX25L3235E
URSA_FLASH_MX(MULTI)
3
WP/SIO2
2
SO/SIO1
4
GND
1
CS
5
SI/SIO0
6
SCLK
7
HOLD/SIO3
8
VCC
R13001
10K
OPT
R13204
33
R13219
33
R13236
100K
R13229
100K
URSA_RESET_READY
R13242
0
OPT
SW13201
1 2
4 3
Slave (Debug Port:0XB4,ISP:0X98)
SPI Flash
0/1/0
Not Used Net (UB85/95/UC89)
Chip Config
0/0/0
BIT [2/1/0]
Debugging for URSA9
Module Type
URSA9_Vx1_RX_HTPD_GPIO
1/0/0
0/0/1
FHD@60 (2lane)
1/1/0
CHIP_CONF=3’d7:111:boot from SPI Flash
URSA Reset
Reserved
Reserved
URSA Option
5k@120 (20lane)
0/1/1
Debug/ISP ADDR
FHD@120 (4lane)
4k@60 (8lane)
Clock for URSA9
1/1/1
CHIP_CONF:{DIM2,DIM1,DIM0}
4K@120 (16lane)
I2C_S Port
Tx Lane
1/0/1
2014.04.24
URSA9 UART1_RX
Change pin from A5 to C4
OLED ULTRA HD
U_UART_GPITO
M1A_URSA9_UD
132
8 Division
0/0
2 Division
Module Division
1/0 4 Division
1/1
Non Division
0/1
BIT [1/0]
Tx Lane
Rx Interface
Division Type
Reserved
Reserved
Module Division OPT
Used net when HDMI SWITCH not used
URSA_BIT1_0
URSA_BIT1_1 URSA_BIT2_1
URSA_BIT2_0
URSA_RX_LVDS
URSA_RX_Vx1
Copyright ⓒ 2015 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only