THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
M14-Peripheral
EB_DATA[0]
EB_ADDR[2]
EB_ADDR[5]
EMMC_DATA[4]
EMMC_DATA[2]
EB_ADDR[9]
EB_ADDR[6]
EB_ADDR[7]
EMMC_DATA[7]
EB_ADDR[14]
EMMC_DATA[0]
EB_ADDR[0]
EB_DATA[3]
EB_DATA[6]
EB_DATA[7]
EMMC_DATA[3]
EB_ADDR[10]
EB_ADDR[8]
EB_ADDR[13]
EMMC_DATA[6]
EB_ADDR[1]
EMMC_DATA[5]
EB_ADDR[11]
EB_DATA[4]
EB_ADDR[12]
EB_ADDR[4]
EB_ADDR[3]
EB_DATA[5]
EB_DATA[1]
EMMC_DATA[1]
EB_DATA[2]
TCK0
EB_WE_N
CAM_WAIT_N
EB_BE_N1
EB_DATA[0-7]
L/DIM0_MOSI (TDO0)
/PCM_CE2
+3.3V_NORMAL
PCM_RESET
CAM_CD1_N
R162
3.3K
EB_BE_N1
PLLSET0
I2C_SDA5
R155
3.3K
TP104
/USB_OCD2
OPM0
TRST_N1
R171
200
1%
SOC_TX
EB_OE_N
PCM_RESET
TP117
EB_BE_N0
WIFI_DP
TP114
JTAG_SOC_RESET
TP108
TP106
TP113
P103
12505WS-10A00
JTAG_CPU
1
2
3
4
5
6
7
8
9
10
11
CAM_INPACK_N
L/DIM0_SCLK
R128
3.3K
USB_DP2
TDI0
USB_DM2
CAM_REG_N
PCM_5V_CTL
OPM1
TP102
EB_DATA[0-7]
OPM0
R108
33
TRST_N1
/PCM_CE2
I2C_SCL3
I2C_SCL2
/PCM_CE1
I2C_SDA6
OPM1
/PCM_CE1
PLLSET0
TP105
I2C_SDA2
CAM_IREQ_N
R161
3.3K
R107
33
R172
200
1%
CAM_REG_N
PLLSET1
EMMC_RST
XTAL_OUT
I2C_SDA3
TP111
P104
12505WS-10A00
OPT
1
2
3
4
5
6
7
8
9
10
11
SOC_RX
I2C_SCL2
XTAL_IN
EMMC_CMD
PCM_5V_CTL
TP103
TP112
TP107
CAM_INPACK_N
AR101
33
TCK0
I2C_SDA2
USB_CTL2
BOOT_MODE
EB_ADDR[0-14]
X101
24MHz
4
GND_2
1
X-TAL_1
2
GND_1
3
X-TAL_2
JTAG_SOC_RESET
R158
3.3K
I2C_SCL1
I2C_SDA1
R178
33
PLLSET1
I2C_SCL5
L/DIM0_VS (TRST0_N)
EB_WE_N
EB_OE_N
CAM_CD1_N
+3.3V_NORMAL
R157
3.3K
R156
3.3K
CAM_WAIT_N
EB_BE_N0
L/DIM0_SCLK (TMS0)
PWM_DIM2
+3.3V_NORMAL
EB_ADDR[0-14]
CAM_CD2_N
R102
3.3K
OPT
R104
3.3K
OPT
L/DIM0_VS
EMMC_DATA[0-7]
I2C_SCL1
R118
1M
BOOT_MODE
R101
3.3K
OPT
L/DIM0_MOSI
EMMC_CLK
I2C_SCL6
R103
3.3K
OPT
TP116
TP109
TP110
CAM_CD2_N
R179
10K
1/16W
5%
TDI0
PWM_DIM
I2C_SDA1
CAM_IREQ_N
R174
200
1%
TP115
WIFI_DM
XTAL_OUT
XTAL_IN
+3.3V_NORMAL
R127
3.3K
OPT
R123
10K
R124
100
R122
10K
Q100
MMBT3904(NXP)
E
B
C
SOC_RESET
+3.3V_NORMAL
R125
OPT
C108
0.1uF
16V
JTAG_SOC_RESET
M_REMOTE_TX
M_REMOTE_RX
I2C_SCL3
I2C_SDA3
I2C_SDA6
I2C_SCL6
R148-*1
1.5K
KR_PIP
R148
3.3K
KR_PIP_NOT
R146-*1
1.5K
KR_PIP
R146
3.3K
KR_PIP_NOT
I2C_SCL5
C107
0.1uF
16V
+3.3V_NORMAL
I2C_SDA5
I2C_SCL5
I2C_SDA5
R109
3.3K
+3.3V_NORMAL
R110
3.3K
R180
560
R111
10K
OPT
R112
10K
OPT
I2C_SCL4
I2C_SDA4
R114
3.3K
R113
3.3K
I2C_SCL4
I2C_SDA4
IC103-*1
M24256-BRMN6TP
NVRAM_ST
3
E2
2
E1
4
VSS
1
E0
5
SDA
6
SCL
7
WC
8
VCC
IC103
AT24C256C-SSHL-T
NVRAM_ATMEL
3
A2
2
A1
4
GND
1
A0
5
SDA
6
SCL
7
WP
8
VCC
FORCED_JTAG_0
R184
10K
R182
OPT
R183
10K
FORCED_JTAG_0
R185
10K
IRB_SPI_SS/TMS1
IRB_SPI_MOSI/TDO1
IRB_SPI_MISO/TDI1
IRB_SPI_CK/TCK1
IRB_SPI_MISO/TDI1
IRB_SPI_MOSI/TDO1
IRB_SPI_CK/TCK1
IRB_SPI_SS/TMS1
USB_DM3
USB_DP3
/USB_OCD3
USB_CTL3
C102
10pF
C101
10pF
+3.3V_TU
IC101
LG1311-C1
XIN_MAIN
B23
XO_MAIN
A23
PORES_N
AG21
BOOT_MODE
AJ18
PLLSET0
AB8
PLLSET1
AC8
OPM0
AD8
OPM1
AE8
L_VSOUT_LD/TRST0_N
Y7
DIM0_SCLK/TMS0
Y6
DIM1_SCLK/TCK0
W7
DIM1_MOSI/TDI0
W6
DIM0_MOSI/TDO0
W5
SPI_CS0
AG30
SPI_SCLK0
AG28
SPI_DO0
AG29
SPI_DI0/TRST1_N
AH29
SPI_CS1/TMS1
AJ27
SPI_SCLK1/TCK1
AH27
SPI_DO1/TDO1
AG26
SPI_DI1/TDI1
AH26
EXT_INTR0
AJ12
EXT_INTR1
AJ13
EXT_INTR2
AH12
EXT_INTR3
AG12
UART0_RXD
AH23
UART0_TXD
AG22
UART1_RXD
AH7
UART1_TXD
AJ7
UART1_RTS_N
AG8
UART1_CTS_N
AH8
SCL0
AH11
SDA0
AG11
SCL1
AH9
SDA1
AG9
SCL2
AG10
SDA2
AJ9
SCL3
AH22
SDA3
AJ22
SCL4
AH10
SDA4
AJ10
SCL5
AG23
SDA5
AH24
PWM0
AC6
PWM1
AC7
PWM2
AD7
PWM_IN
AB7
EMMC_CLK
G32
EMMC_CMD
G33
EMMC_RESETN
G31
EMMC_DATA7
D31
EMMC_DATA6
F33
EMMC_DATA5
F32
EMMC_DATA4
E32
EMMC_DATA3
F31
EMMC_DATA2
D33
EMMC_DATA1
D32
EMMC_DATA0
E31
USB2_0_DP0
AN9
USB2_0_DM0
AM9
USB2_0_TXRTUNE
AN8
USB2_1_DP0
H32
USB2_1_DM0
J31
USB2_1_TXRTUNE
H33
USB3_DP0
N31
USB3_DM0
N32
USB3_TXP0
P33
USB3_TXM0
P32
USB3_RXP0
M32
USB3_RXM0
M33
USB3_RESREF0
P31
USB3_DP1
K33
USB3_DM1
K32
USB3_TXP1
L32
USB3_TXM1
L31
USB3_RXP1
K31
USB3_RXM1
J32
USB3_RESREF1
M31
HUB_PORT_OVER0
W28
HUB_VBUS_CTRL0
W29
EB_CS3
H28
EB_CS2
J30
EB_CS1
J28
EB_CS0
J29
EB_WE_N
G30
EB_OE_N
F30
EB_WAIT
H29
EB_BE_N1
G29
EB_BE_N0
G28
CAM_CD1_N
P28
CAM_CD2_N
P27
CAM_CE1_N
U28
CAM_CE2_N
R29
CAM_IREQ_N
V27
CAM_RESET
T28
CAM_INPACK_N
T29
CAM_VCCEN_N
R28
CAM_WAIT_N
U27
CAM_REG_N
N29
EB_ADDR0
K30
EB_ADDR1
E30
EB_ADDR2
M30
EB_ADDR3
N28
EB_ADDR4
M28
EB_ADDR5
M29
EB_ADDR6
L29
EB_ADDR7
K29
EB_ADDR8
K28
EB_ADDR9
L28
EB_ADDR10
D30
EB_ADDR11
F29
EB_ADDR12
C32
EB_ADDR13
C33
EB_ADDR14
C31
EB_ADDR15
B33
EB_DATA0
B32
EB_DATA1
A32
EB_DATA2
B31
EB_DATA3
A31
EB_DATA4
A30
EB_DATA5
B30
EB_DATA6
C30
EB_DATA7
C29
IC103-*2
BR24G256FJ-3
NVRAM_ROHM
3
A2
2
A1
4
GND
1
A0
5
SDA
6
SCL
7
WP
8
VCC
AR105
33
R130
0
OPT
R131
0
OPT
R132
0
OPT
R133
0
OPT
I2C_SCL3
I2C_SDA3
I2C_SCL4
I2C_SDA4
I2C_SCL_MICOM
I2C_SDA_MICOM
R121
33K
OPT
1
LX770H
2015.3.11
24
M14+ Symbol A
I2C_1 : AMP
I2C_2 : T-CON,L/DIMING
I2C_3 : Pro:idiom , Demod
I2C_4 : RGB Sensor
I2C_5 : NVRAM
I2C_6 : b-LAN / Tuner
Extenal test only
OP MODE[1:0]
"00" : Normal Mode
"01/10/11" : Internal Test mode
Extenal test only
BOOT_MODE0
System Configuration
BOOT MODE
"0 : EMMC
"1 : TEST MODE
System Clock for Analog block(24Mhz)
I2C
I2C PULL UP
MAIN Clock(24Mhz)
Clock for M14+
Jtag-1 I/F
PLL SET[1:0] : internal pull up
"00" : CPU(1200Mhz),M0 / M1 DDR(792,792 Mhz)
"01" : CPU(1056Mhz),M0 / M1 DDR(672,672 Mhz)
"10" : CPU(1056Mhz),M0 / M1 DDR(792,792 Mhz)
"11" : CPU( 960Mhz),M0 / M1 DDR(792,792 Mhz)
Jtag-0 I/F
NVRAM
Write Protection
- Low : Normal Operation
- High : Write Protection
EAX66791501:LA5GG
LX770H-UA:webOS 2.0
Copyright © 2015 LG Electronics Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Summary of Contents for 40LX770H
Page 53: ......
