Lenovo System x3850 X6 and x3950 X6 Quick Start Guide
29
The quick path interconnect (QPI) debug consists of a set of 20 TX lanes plus a CLK and
a set of 20 RX lanes plus a clock. If any one lane fails, the system picks 10 good lanes and
runs in half width. If the clock fails, the system uses one of the data lanes as the CLK and
runs in half width. This
faildown
happens independently on TX and RX. That is, the RX
can run in half width, and the TX port runs in full length. Each CPU has three QPI
interfaces labeled 0, 1, and 2.
In a four-socket or eight-socket system, the QPI meshes all CPUs together, as shown in
Figure 29 and Figure 30.
Figure 29 Four-socket system QPI topology
Figure 30 Eight-socket system QPI topology
QPI
Port 2
QPI
Port 2
QPI
Port 2
QPI
Port 2
Four-socket
QPI topology
CPU1
CPU2
CPU3
CPU4
QPI
Port 1
QPI
Port 1
QPI
Port 1
QPI
Port 1
QPI
Port 0
QPI
Port 0
QPI
Port 0
QPI
Port 0
QPI
Port 1
QPI
Port 0
QPI
Port 2
CPU5
QPI
Port 1
QPI
Port 1
QPI
Port 1
QPI
Port 1
QPI
Port 1
QPI
Port 1
QPI
Port 1
QPI
Port 0
QPI
Port 0
QPI
Port 0
QPI
Port 0
QPI
Port 0
QPI
Port 0
QPI
Port 0
QPI
Port 2
QPI
Port 2
QPI
Port 2
QPI
Port 2
QPI
Port 2
QPI
Port 2
QPI
Port 2
CPU6
CPU7
CPU8
CPU1
CPU2
CPU3
CPU4
Eight-socket
QPI topology
