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Lavry DA924, Operation Manual

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DA924

Operations Manual

8

using varispeed, thus its use should be restricted for sample rates outside of the narrow
lock range. Some multi-channel uses of the DA924 may require varispeed for
synchronization.

To enable wide lock, press and hold the POLARITY button for 1.5 seconds. To return to
CrystalLock™, press and hold the POLARITY button again. The unit indicates
varispeed mode by blinking the appropriate status light periodically. This mode setting is
retained when power is removed.

Summary of Contents for DA924

Page 1: ...on Digital to Analog Converter Operations Manual Lavry Engineering Inc 824 Post Avenue Seattle WA 98104 206 381 5891 http www lavryengineering com E Mail info lavryengineering com Revision 1 1 March 1998 E LAVRY ENGINEERING I I ...

Page 2: ...r or personnel Lavry Engineering reserves the right to deny warranty service to products that have been used in rental service bureau or similar businesses This limited warranty gives you specific legal rights You may have others which vary from state jurisdiction to state jurisdiction LIMITS AND EXCLUSIONS LAVRY ENGINEERING DOES NOT BY VIRTUE OF THIS AGREEMENT OR BY ANY COURSE OF PERFORMANCE COUR...

Page 3: ...Input signal connection 5 Analog Outputs 6 Analog Output Level Adjustment 6 Turn On sequence 7 Polarity inversion 7 CrystalLock and Wide lock 7 Part II Theory of operation 9 Oven control 9 Calibration 9 Timing and deglitcher 10 Jitter removal 11 Output filter and drivers 11 Power and Fusing 11 Maintenance 12 Part III Specifications 13 ...

Page 4: ...rovides superior low level detail by keeping low level signals away from the most significant bit transitions A quad switch deglitcher circuit removes the unwanted transition glitch energy The DA924 eliminates jitter in the incoming data stream by use of a DSP controlled pullable crystal oscillator and a short buffer memory for temporary storage of the incoming data The DSP transfers the data from...

Page 5: ... the INPUT SELECT button for more then a second makes the DA924 go into search mode the unit will step through the inputs but will skip the inactive input connectors where no signal is present Holding the INPUT SELECT button for more than one second switches between manual input selection and the input search mode or visa versa The mode selected is retained when power is removed Input signal conne...

Page 6: ... hooked for balanced output the full scale analog level can be adjusted between 12dBu to 22dBu When hooked for Unbalanced output the full scale analog level can be adjusted between 6dBu to 16dBu The IEC connector level is adjustable between 8dBu and 8dBu full scale signal The wide 0 10dB attenuation range relies on an internal pot When operating at minimum attenuation 22dBu balanced or 16dBu unbal...

Page 7: ... on The DA924 turn on spike may be higher then that found in other DACs but the sound is not compromised The spike due to power off is comparable to that found in other DACs Polarity inversion The normal polarity is set to pin 3 hot To invert press the POLARITY switch Signal inversion is indicated by a lit INVERT lamp Inverting while in unbalanced operation impacts signal polarity on the IEC cente...

Page 8: ...nnel uses of the DA924 may require varispeed for synchronization To enable wide lock press and hold the POLARITY button for 1 5 seconds To return to CrystalLock press and hold the POLARITY button again The unit indicates varispeed mode by blinking the appropriate status light periodically This mode setting is retained when power is removed ...

Page 9: ...age difference between any given network node and the reference is greatly amplified and then fed to a strobing comparator see multiplexers for calibration and error amplifier and comparator gain blocks in the simplified diagram The processor strobes the comparator and reads its output The strobing is repeated 4000 times for the sake of averaging out any error due to amplifier noise At the end of ...

Page 10: ...the analog circuits The settled signals are fed to the output filter with minimum disturbance The deglitcher off time settling requires the circuit to block as much of the transitions from feeding forwards to the output filter The blocking requirement is very demanding because a transition of many volts between two adjacent sample values should feed forward less than a micro volt A single switch c...

Page 11: ... 100ppm per second input rate step requires pre storage of about 5 words of data for 1 second D A stepping or an 50 word memory for 10 seconds of D A update rate Output filter and drivers The DA924 operates in low oversampling to allow for maximum settling time of the DAC circuits and to further reduce sensitivity to jitter The upsampling filter is calculated by the DSP The tradeoff in favor of lo...

Page 12: ...DA924 Operations Manual 12 The front panel is gold plated 24 karat gold Use a soft cloth and plain water if necessary to clean finger prints ...

Page 13: ...speed Crystal lock tracking 1ppm 15 seconds Channel separation 100dBFs at 1KHz Flatness response 05dB 10Hz 20KHz Phase linearity 2 degrees 10Hz 20 KHz Digital inputs two AES EBU 110 Ohm transformer isolated one Consumer 75 Ohm transformer isolated Analog outputs AES EBU balanced 22dBuFS into 600 ohms Max 12dBuFS Min AES EBU unbalanced 16dBuFS into 600 ohms Max 6dBuFS Min Consumer outputs 8 5dBuFS ...

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