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PQIII Debugger | 3
©
1989-2021
Lauterbach GmbH
Multicore Debugging e500 cores
Synchronous stop of both e500 cores
Programming Flash on MPC85XX / QorIQ P10XX/P20XX, PSC93XX
On-chip Trace on MPC85XX/QorIQ
PowerPC MPC85XX/QorIQ specific SYStem Commands ..............................................
Configure debugger according to target topology
Control pin 8 of debug connector
Configure driver strength of TCK pin
Lock and tristate the debug port
Run-time memory access (non-intrusive)
Enable debugging of critical interrupts
Prevent data cache line load/flush in debug mode
Implicitly use run-time memory access
Freeze system timers on debug events
Invalidate instruction cache before go and step
Disable interrupts while single stepping
Disable interrupts while HLL single stepping
Separate address spaces by space IDs
Disable JTAG stop on debug events
Use alternative software breakpoint instruction
Stop on-chip peripherals in debug mode
Set behavior when target reset detected
Use alternative method for ASM single step
Page wise display of MMU translation table