PQIII Debugger | 34
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1989-2021
Lauterbach GmbH
If OFF, the debugger will maintain D/L2 cache coherency by performing cache snoops for memory
accesses. During the cache snoop, the processor will flush (clean and invalidate) dirty lines from data
caches before the debugger’s memory access takes place. This setting allows better data throughput and is
recommended for normal application level debugging. In order to see changes to the cache state caused by
debugging in the
If ON, the debugger will maintain cache coherency by reading or writing directly to the cache arrays. This
method guarantees that the D/L2 cache tags and status bits (valid, dirty) remain unaffected by the memory
accesses of the debugger. This setting is recommended for low-level and cache debugging.
SYStem.Option.DCREAD
Read from data cache
Default: ON. If enabled,
windows for access class D: (data) and variable windows display the
memory values from the d-cache or L2 cache, if valid. If data is not available in cache, physical memory will
be read.
SYStem.Option.DUALPORT
Implicitly use run-time memory access
Forces all list, dump and view windows to use the access class
E:
(e.g.
E:
0x100) or to use the
format option
%E
(e.g.
%E
var1) without being specified. Use this option if you want all windows to
be updated while the processor is executing code. This setting has no effect if
is disabled or real-time memory access not available for used CPU.
Please note that while the CPU is running, MMU address translation can not be accesses by the debugger.
Only physical addresses accesses are possible. Use the access class modifier “A:” to declare the access
physical addressed, or declare the address translation in the debugger-based MMU manually using
Format:
SYStem.Option.DCREAD
[
ON
|
OFF
]
Format:
SYStem.Option.DUALPORT
[
ON
|
OFF
]
