MicroBlaze Debugger and Trace | 15
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1989-2021
Lauterbach GmbH
Breakpoints
There are two types of breakpoints available:
•
Software breakpoints (SW-BP) and
•
Onchip breakpoints.
Software Breakpoints
Software breakpoints are implemented via a breakpoint instruction. These are the default breakpoints and
are usually used in RAM areas. Utilizing advanced TRACE32 mechanisms, in software breakpoints can
also be used in FLASH areas.There is no restriction in the number of software breakpoints.
For using SW breakpoints with ucLinux or other operating systems, setting the option
may be required.
On-chip Breakpoints
Onchip breakpoints (Lauterbach terminology) allow to stop the core in specific conditions. As this is
implemented via hardware-resources, they are also referred to as “hardware breakpoints” in non-
Lauterbach terminology.
The following list gives an overview of the usage of the on-chip breakpoints by TRACE32-ICD:
•
Instruction breakpoints
stop the core when it reaches a certain program location.
•
Read/Write address breakpoints
can stop the core upon read or write data accesses.
•
Data breakpoints
stop the program when a specific data value is written to an address or when
a specific data value is read from an address.
Breakpoints in ROM
With the command
, TRACE32 is configured to use onchip breakpoints in
the specified address range. Therefore the command
will set an onchip breakpoint in this range
and the parameter
/Onchip
can be omitted. Typically this feature is used with ROM or FLASH memories
that prevent the use of software breakpoints.
NOTE:
The number of available onchip breakpoints depends on the configuration of the
MicroBlaze core defined in the FPGA design.
