MIPI D-PHY Bandwidth Matrix Table
User Guide
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FPGA-UG-02041-1.1
17
Notes
:
1.
Rx and Tx Performance is calculated from the data sheet External Timing Table using IDDRX2/X4/X8 and ODDRX2/X4/X8with
data and clock centered aligned. See the
section for the calculations based on current data sheet.
Re-calculate to confirm these values with the most up to date data sheet specification
2.
If LVCMOS33D is used instead of LVDS25E, external resistors shown in
should be adjusted to modulate
common mode voltage level.
3.
CrossLink has two hardened MIPI IPs on the top side of the chip, and has dedicated IO associated with harded IP. Regard to
MIPI D-PHY interface implementation, on the receiver side it has hardened IP offering as well as soft IP offering, but on the
transmitter side it only offers hardened IP implemtation.
