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HDMI Mezzanine Card – Revision B
User’s Guide
Figure 3. HDMI Mezzanine Card Installed on the LatticeECP3 Video Protocol Board
Header Settings
This section describes the header settings on the HDMI Mezzanine Card. However, since the card uses SERDES
quad C when plugging into the LatticeECP3 Video Protocol Board, the VCCOB and the VCCIB of SERDES quad C
need to be powered properly. Please make sure shuts are installed on J18 and J22 of the LatticeECP3 Video Pro-
tocol Board.
As mentioned previously, the selection of the two HDMI/DVI inputs is done by a 3-pin header. Table 1 shows the
locations of where the shunt should be installed.
Table 1. MUX Selection Control
HDMI/DVI
Input
Mode
MUX Select
Shunt Installation
on H13
J1
Equalized HDMI/DVI Input
High
Pin 1/Pin 2
J2
Non-Equalized HDMI/DVI Input
Low
Pin 2/Pin 3
Other than the TMDS clock and data pairs, the HDMI/DVI interface includes CEC, HPD and the DDC clock and
data signals. By installing shuts on different locations of the 12 headers, these signals can be selected to be
bypassed from the HDMI/DVI input to the HDMI/DVI output, or they can be selected to be connected to the
LatticeECP3 FPGA on the LatticeECP3 Video Protocol Board.
Figure 4 shows the locations of these 12 headers on the HDMI Mezzanine Card and the signals these headers
control. The 12 headers are divided into four groups as shown in Figure 4. Each group includes three headers for
controlling one of the four signals. The black square is used to indicate pin 1 of each header.
