3
HDMI Mezzanine Card – Revision B
User’s Guide
nals is different from the SERDES CML signals, and the TMDS coding scheme maintains the DC balance of the
signal, the AC coupling capacitors are used to block the DC component of the driving signal.
Figure 2 shows the functional block diagram of the HDMI Mezzanine Card. For validation purposes, this card is
designed to include two HDMI/DVI input ports. One of these input paths has a TMDS cable equalizer and the other
does not. The signals of both paths will go into the 2-to-1 TMDS MUX, then the AC coupling capacitors to the
SERDES input pins. Depending on which pins a shunt is installed on a 3-pin header, one of the two inputs will be
selected and the signals will be fed to the SERDES.
For meeting the HDMI/DVI’s strict electrical compliance test specification, a TMDS level shifter is added to the out-
put path. This level shifter can be removed if the design does not have this requirement. The ESD protector is
added on both the input and output HDMI/DVI ports. Other than the HDMI/DVI, an S/PDIF input interface is also
included for bringing in a digital audio stream through the TOSLINK connector.
Figure 2. Functional Block Diagram
Regular
100-mil
Connector
10 Gbps Mezzanine Connector
AC Coupling
Data Pairs
Data Pairs
Clock
Data Pairs
Clock
Data Pairs
Clock
Data Pairs
Clock
Clock
2
2
2
2
6
2
6
6
6
2
6
6
AC Coupling
TMDS
2:1 Switch
(PI3HDMI1210-A)
4 Gbps
TMDS
Equalizer
(STDVE001)
3.4 Gbps
ESD
Protector
ESD
Protector
ESD
Protector
S/PDIF
TORX147
Output
Input 2
Input 1
TMDS Clock
TMDS
Level Shifter
(STHDLS101T)
3.4 Gbps
Figure 3 shows the HDMI Mezzanine Card installed on the LatticeECP3 Video Protocol Board. The two cables are
the HDMI cables connecting to J1 (HDMI/DVI input) and J3 (HDMI/DVI output) of the daughter card. A 12 mm tall
standoff is recommended for securing the HDMI Mezzanine Card on the LatticeECP3 Video Protocol Board
through screws.
