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LFE2-50E-VID-EV
Page 1: ...tion HDL source and bitstream programming files for the LatticeECP2 FPGA a user s guide for the LatticeECP2 Advanced Evaluation Board and other related materials can be downloaded from the Lattice web...
Page 2: ...rialized and transmitted via the LatticeECP2 50 LVDS I Os The remainder of the setup is similar to the video input side but reversed The LVDS signals are fed via a VHDM connector to the Video Demo boa...
Page 3: ...board1 1 2 5V wall mount power adapter1 1 3 Video Demo board 1 1 4 Video Demo board 42 1 5 Video Demo board 2 1 6 Video Demo board 3 1 7 DVI cable 1 8 MDR 26 Channel Link cable 2 9 Black banana plug...
Page 4: ...n pin1 pin2 of J3 J7 J8 J9 J11 J13 and J21 Install jumpers on pin2 pin3 of J10 and J12 Install jumpers on pin1 pin3 of J4 and J6 Install jumper on pin4 pin6 of J5 RS 232 LatticeECP2 50 672 fpBGA LCD 1...
Page 5: ...e set to 3 3V The following table shows the proper jumper settings for the Lattice 7 1 Video Demo Table 2 Jumper Settings for the LatticeECP2 Advanced Board sysIO Bank Jumper Jumper on Pins 0 J14 1 3...
Page 6: ...llator clock output to the LatticeECP2 50 device The locations of these jumpers are shown below Figure 5 Jumper Settings on the LatticeECP2 Advanced Evaluation Board If you are using the optional CP 2...
Page 7: ...Board Figure 6 shows the proper installation of Board 1 Tx side on the left and Board 4 Rx side on the right installed on the LatticeECP2 Advanced Evaluation Board Note in this figure the Board 4 sho...
Page 8: ...m if it is not get ting a proper EDID from the video sink To prevent this from happening you should first set the screen resolution and check if the video stream is transmitting properly to the LCD di...
Page 9: ...lected the push button SW4 needs to be toggled to activate the adjustment Note that once the Auto Demo is enabled the OSD will be moving its position and bounce back when it hits the edge of the displ...
Page 10: ...o Demo Kit at www latticesemi com boards Figure 9 is a representation of the top level VHDL file of this design The gray color blocks shown below are imple mented in other VHDL files The light green c...
Page 11: ...real number 1 0 is represented by the 9 bit binary 100000000 The maximum value of the gains are limited to 1 0 The product of the 9x9 multiplier is an 18 bit value with 10 integer part bits and 8 frac...
Page 12: ...The 4 bit outputs of the serializers are sent to the 2x gearing ODDRX2B modules for pumping out of the LVDS I Os For more information about the transmitter please refer to Lattice reference design RD1...
Page 13: ...d are not compatible Please use a standard DVI source such as a laptop or desktop computer or a Channel Link source to the LVDS No video output when everything is connected There are a number of possi...
Page 14: ...by the Lattice Power Manager II POWR1220AT8 If SW1 Pin 1 is on pushed down the POWR1220AT8 device will be reset and all powers including the 3 3V will be disabled 5 The monitor being used is a VGA mon...
Page 15: ...latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notic...
Page 16: ...input of TFP410 Pin1 and Pin2 high J9 DKEN Data de skew enable control of TFP410 Pin1 and Pin2 high J10 ISEL RSTn This is an active high I2 C select signal of TFP410 used for enabling the TFP410 s I2...
Page 17: ...QO 23 0 and control signals HSYNC VSYNC DE CTL1 3 are latched Pin1 and Pin2 high J6 DFO TFP401A s Output clock data format Controls the output clock ODCK format for either TFT or DSTN panel support P...
Page 18: ...emo Board 1 Figure 14 Video Demo Board 1 Schematic 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Title Size Document Number Rev Date Sheet of A Video Demo Board 1 C 1 2 Title Size Document Number Rev Date Sheet...
Page 19: ...14 TxOut0Gnd 2 TxOut0 15 Sense 3 USB DDC_Gnd 16 TxOut1 4 TxOut1Gnd 17 TxOut1 5 DDC SDA 18 TxOut2 6 TxOut2Gnd 19 TxOut2 7 USB 20 USB_Shield 8 USB 21 DDC SCL 9 TxClkOut 22 TxClkOutGnd 10 TxClkOut 23 USB...
Page 20: ...mo Board 2 Schematic 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Title Size Document Number Rev Date Sheet of A Video Demo Board 2 C 1 2 Title Size Document Number Rev Date Sheet of A Video Demo Board 2 C 1 2...
Page 21: ...PV37W101C01 PV37W 1 3 2 C4 0 001uF 0603 C4 0 001uF 0603 J15 HEADER 10X2 J15 HEADER 10X2 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 C23 0 1uF 0603 C23 0 1uF 0603 C14 0 1uF 0603 C14 0 1uF 0603 C...
Page 22: ...mo Board 3 Schematic 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Title Size Document Number Rev Date Sheet of A Video Demo Board 3 C 1 2 Title Size Document Number Rev Date Sheet of A Video Demo Board 3 C 1 2...
Page 23: ...R11 0 0603 R11 0 0603 C17 22uF 1206 C17 22uF 1206 J15 HEADER 10X2 J15 HEADER 10X2 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 DVI Integrated J1 DVI_I DVI Integrated J1 DVI_I TMDS_Data2 2 TMDS_D...
Page 24: ...o Board 4 Schematic 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Title Size Document Number Rev Date Sheet of A1 Video Demo Board 4 C 1 2 Title Size Document Number Rev Date Sheet of A1 Video Demo Board 4 C 1...
Page 25: ...Shield 19 USB 7 RxIn2 20 RxIn2Gnd 8 RxIn2 21 DDC SDA 9 RxIn1 22 RxIn1Gnd 10 RxIn1 23 USB DDC_Gnd 11 Sense 24 RxIn0 12 RxIn0Gnd 25 RxIn0 13 DDC_Gnd_26 26 Mounting_R 27 Mounting_L 28 J1 MOLEX VHDM 74031...
Page 26: ...Demo Board 1 is not equivalent to Video Demo Board 4 Please modify the lpf preference file of reference design RD1030 LatticeECP2 M 7 1 LVDS Video Interface to match the board that you are using on th...
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