background image

 

23

 

Lattice 7:1 LVDS Video Demo Kit

Lattice Semiconductor

User’s Guide

 

Figure 14. Video Demo Board #3 Schematic (Cont.)

5

5

4

4

3

3

2

2

1

1

D

D

C

C

B

B

A

A

T

M

D

S

_D

AT

A0_N

T

M

D

S

_D

AT

A0_P

T

M

D

S

_D

AT

A1_P

T

M

D

S

_D

AT

A1_N

T

M

D

S

_D

AT

A2_P

T

M

D

S

_D

AT

A2_N

T

M

D

S

_C

LK_N

T

M

D

S

_C

LK_P

TI

_

P

V

D

D

DV

DD

OC

K_I

N

V

DFO

PI

XS

ST

AGN

ST

PD

N

PD

ON

VC

C

_

3.

3V

TI

_

A

V

D

D

TI

_

O

V

D

D

NS

_

L

V

C

C

NS

_

P

V

C

C

DV

DD

TX

_

O

U

T

0

_

P

TX

_

O

U

T0

_

N

TX

_

O

U

T

1

_

N

TX

_

O

U

T2

_

P

TX

_

O

U

T

2

_

N

TX

_

O

U

T1

_

P

TX

_

O

U

T3

_

P

TX

_

O

U

T3

_

N

TX

_

C

L

K

O

U

T_

P

TX

_

C

L

K

O

U

T_

N

TI

_

A

V

D

D

DV

DD

DV

DD

TI

_

O

V

D

D

TI

_

P

V

D

D

N

S_LVC

C

N

S

_PVC

C

OC

K_I

N

V

DV

DD

DV

DD

DFO

DV

DD

PI

XS

DV

DD

ST

AGN

DV

DD

PD

N

DV

DD

DV

DD

PD

ON

SC

D

T

ST

DV

DD

TX

IN

2

7

TX

IN

2

6

TX

IN

2

5

TX

IN

2

4

TX

IN

2

3

TX

IN

2

2

TX

IN

2

1

TX

IN

2

0

TX

IN

1

9

TX

IN

1

8

TX

IN

1

7

TX

IN

1

6

TX

IN

1

5

TX

IN

1

4

TX

IN

1

3

TX

IN

1

2

TX

IN

1

1

TX

IN

1

0

TX

IN

9

TX

IN

8

TX

IN

7

TX

IN

6

TX

IN

5

TX

IN

4

TX

IN

3

TX

IN

2

TX

IN

1

TX

IN

0

TX

C

L

K

IN

TXIN0

TXIN1

TXIN3 
TXIN2

TXIN5

TXIN7 
TXIN6

TXIN4

TXIN9

TXIN1

1

TXIN1

0

TXIN1

3

TXIN1

5

TXIN1

4

TXIN1

2

TXIN8

TXIN1

7

TXIN1

9

TXIN1

8

TXIN2

1

TXIN2

3

TXIN2

2

TXIN2

0

TXIN1

6

TXIN2

5

TXIN2

7

TXIN2

6

TXCL

KIN

TXIN2

4

TX

IN

7

TX

IN

1

8

TX

IN

1

5

TX

IN

1

4

DV

DD

PW

R

D

W

N

VC

C

_

3.

3V

TXCL

KIN

TXIN1

TXIN3

TXIN2

TXIN5

TXIN7

TXIN6

TXIN4 
TXIN0

TXIN9

TXIN1

1

TXIN1

0

TXIN1

3

TXIN1

5

TXIN1

4

TXIN1

2

TXIN8

TXIN1

7

TXIN1

9

TXIN1

8

TXIN2

1

TXIN2

3

TXIN2

2

TXIN2

0

TXIN1

6

TXIN2

5

TXIN2

7

TXIN2

6

TXIN2

4

Ti

tl

e

S

ize

Do

cu

m

e

n

t Nu

m

b

e

r

Re

v

Da

te

:

S

h

e

e

t

of

A

DVI to Channel

 Li

nk

C

22

Ti

tl

e

S

ize

Do

cu

m

e

n

t Nu

m

b

e

r

Re

v

D

a

te

:

S

h

e

et

of

A

DVI to Channel

 Li

nk

C

22

Ti

tl

e

S

ize

Do

cu

m

e

n

t Nu

m

b

e

r

Re

v

D

a

te

:

S

h

e

et

of

A

DVI to Channel

 Li

nk

C

22

Lattice Semiconductor Corporation

LED will be ON

when link is

active.

(SCDT high)

Gate

Source

Drain

SOT-23

Drain

Source

Gate

R

G

B

LVDS pairs

TMDS pairs

C5

22uF

1206

C5

22uF

1206

R7

10K

0603

R7

10K

0603

J8

HE

A

D

E

R

 3

J8

HE

A

D

E

R

 3

1

2

3

C2

8

0.

01uF

0603

C2

8

0.

01uF

0603

R1

10K

0603

R1

10K

0603

C2

3

0.

01uF

0603

C2

3

0.

01uF

0603

J1

0

HE

A

D

E

R

 3

J1

0

HE

A

D

E

R

 3

1

2

3

R1

4

0

0603

R1

4

0

0603

C2

2

0.

1uF

0603

C2

2

0.

1uF

0603

J1

7

B

A

NA

NA

 JA

CK

J1

7

B

A

NA

NA

 JA

CK

S

1

J1

9

3M

_T

x

_

10226-

1

210VE

J1

9

3M

_T

x

_

10226-

1

210VE

DDC_

G

n

d

_

1

1

TxO

u

t0

-

14

T

x

Out

0

Gnd

2

TxO

u

t0

+

15

Se

ns

e

3

US

B

/DDC_

G

n

d

16

TxO

u

t1

-

4

T

x

Out

1

Gnd

17

TxO

u

t1

+

5

DDC/S

D

A

18

TxO

u

t2

-

6

T

x

Out

2

Gnd

19

TxO

u

t2

+

7

US

B

+

20

US

B

_

S

h

ie

ld

8

US

B

-

21

DDC/S

C

L

9

TxC

lk

O

u

t-

22

TxC

lk

O

u

tG

n

d

10

TxC

lk

O

u

t+

23

U

S

B_+

5VD

C

11

DDC_

+

5

V

D

C

24

TxO

u

t3

-

12

T

x

Out

3

Gnd

25

TxO

u

t3

+

13

D

D

C

_

Gnd_26

26

Mo

u

n

ti

n

g

_

R

27

Mo

u

n

ti

n

g

_

L

28

R5

10K

0603

R5

10K

0603

J7

HE

A

D

E

R

 3

J7

HE

A

D

E

R

 3

1

2

3

C7

0.

01uF

0603

C7

0.

01uF

0603

C2

9

0.

1uF

0603

C2

9

0.

1uF

0603

C6

0.

1uF

0603

C6

0.

1uF

0603

R1

2

0

0603

R1

2

0

0603

R1

3

470

0603

R1

3

470

0603

C9

22uF

1206

C9

22uF

1206

J6

HE

A

D

E

R

 3

J6

HE

A

D

E

R

 3

1

2

3

R8

10K

0603

R8

10K

0603

C4

0.

001uF

0603

C4

0.

001uF

0603

C8

0.

001uF

0603

C8

0.

001uF

0603

J1

4

HE

A

D

E

R

 1

0

X

2

J1

4

HE

A

D

E

R

 1

0

X

2

1

3

5

7

9

11

13

15

17

19

2

4

6

8

10

12

14

16

18

20

C1

1

0.

01uF

0603

C1

1

0.

01uF

0603

C1

0

0.

1uF

0603

C1

0

0.

1uF

0603

J3

HE

A

D

E

R

 3

X

2

J3

HE

A

D

E

R

 3

X

2

2

4

6

1

3

5

J1

8

B

A

NA

NA

 JA

CK

J1

8

B

A

NA

NA

 JA

CK

S

1

C2

0.

1uF

0603

C2

0.

1uF

0603

C1

2

0.

001uF

0603

C1

2

0.

001uF

0603

J1

1

HE

A

D

E

R

 3

J1

1

HE

A

D

E

R

 3

1

2

3

C1

3

22uF

1206

C1

3

22uF

1206

J4

HE

A

D

E

R

 3

J4

HE

A

D

E

R

 3

1

2

3

C1

6

0.

001uF

0603

C1

6

0.

001uF

0603

R2

4

7

0

0603

R2

4

7

0

0603

D2

LED

_

R

e

d

D2

LED

_

R

e

d

R1

5

0

0603

R1

5

0

0603

R6

10K

0603

R6

10K

0603

C2

0

0.

001uF

0603

C2

0

0.

001uF

0603

J1

3

HE

A

D

E

R

 1

0

X

2

J1

3

HE

A

D

E

R

 1

0

X

2

1

3

5

7

9

11

13

15

17

19

2

4

6

8

10

12

14

16

18

20

C1

5

0.

01uF

0603

C1

5

0.

01uF

0603

C1

4

0.

1uF

0603

C1

4

0.

1uF

0603

R9

10K

0603

R9

10K

0603

C2

4

0.

001uF

0603

C2

4

0.

001uF

0603

+

C2

5

10uF

1206

+

C2

5

10uF

1206

R1

1

0

0603

R1

1

0

0603

C1

7

22uF

1206

C1

7

22uF

1206

J1

5

HE

A

D

E

R

 1

0

X

2

J1

5

HE

A

D

E

R

 1

0

X

2

1

3

5

7

9

11

13

15

17

19

2

4

6

8

10

12

14

16

18

20

DVI-Integrated

J1

DV

I_

I

DVI-Integrated

J1

DV

I_

I

TM

D

S

_

D

a

ta

2

+

2

T

M

D

S

_

D

at

a2

-

1

T

M

D

S

_

D

at

a4

-

4

TM

D

S

_

D

a

ta

4

+

5

TM

D

S

_

D

a

ta

2

/4

_

S

h

ie

ld

3

DDC_

C

lo

ck

6

DDC_

D

a

ta

7

A

n

alog

_

V

ert

ic

a

l_

S

yn

c

8

T

M

D

S

_

D

at

a1

-

9

TM

D

S

_

D

a

ta

1

+

10

TM

D

S

_

D

a

ta

1

/3

_

S

h

ie

ld

11

T

M

D

S

_

D

at

a3

-

12

TM

D

S

_

D

a

ta

3

+

13

+5

V

_

P

o

w

e

r

14

GN

D

(f

o

r +

5

V)

15

Ho

t_

P

lu

g

_

D

e

te

c

t

16

T

M

D

S

_

D

at

a0

-

17

TM

D

S

_

D

a

ta

0

+

18

TM

D

S

_

D

a

ta

0

/5

_

S

h

ie

ld

19

T

M

D

S

_

D

at

a5

-

20

TM

D

S

_

D

a

ta

5

+

21

TM

D

S

_

C

lo

c

k

_

S

h

ie

ld

22

TM

D

S

_

C

lo

c

k

+

23

TM

D

S

_

C

lo

c

k

-

24

Ana

lo

g

_R

e

d

C1

A

n

alog

_

G

reen

C2

Ana

lo

g

_Bl

u

e

C3

A

n

alog

_

H

oriz

on

ta

l_

S

y

n

c

C4

Ana

lo

g

_Gr

o

und_1

C5

Ana

lo

g

_Gr

o

und_2

C6

+

C2

6

0.

1uF

0603

+

C2

6

0.

1uF

0603

D

S

90C

R

287

U2

D

S

90C

R

287

U2

LVD

S

GN

D

43

TxO

U

T3

P

37

TxO

U

T3

N

38

TxO

U

T2

P

41

TxO

U

T2

N

42

TxO

U

T1

P

45

TxO

U

T1

N

46

TxO

U

T0

P

47

TxO

U

T0

N

48

LVD

S

VC

C

44

LVD

S

GN

D

36

LVD

S

GN

D

49

TxC

L

K

O

U

TP

39

TxC

L

K

O

U

T

N

40

PW

R

D

W

N

32

TxI

N

0

51

TxI

N

1

52

TxI

N

2

54

TxI

N

3

55

TxI

N

4

56

TxI

N

5

2

TxI

N

6

3

TxI

N

7

4

TxI

N

8

6

TxI

N

9

7

TxI

N

1

0

8

TxI

N

1

1

10

TxI

N

1

2

11

TxI

N

1

3

12

TxI

N

1

4

14

TxI

N

1

5

15

TxI

N

1

6

16

TxI

N

1

7

18

TxI

N

1

8

19

TxI

N

1

9

20

TxI

N

2

0

22

TxI

N

2

1

23

TxI

N

2

2

24

TxI

N

2

3

25

TxI

N

2

4

27

TxI

N

2

5

28

TxI

N

2

6

30

TxI

N

2

7

50

GN

D

53

GN

D

21

GN

D

29

VC

C

1

GN

D

5

PLLGN

D

35

GN

D

13

PLLVC

C

34

PLLGN

D

33

VC

C

9

VC

C

17

VC

C

26

TxC

L

K

IN

31

J1

6

M

O

LEX VH

D

M

 74057-

1002

J1

6

M

O

LEX VH

D

M

 74057-

1002

A1

A1

A2

A2

A3

A3

A4

A4

A5

A5

A6

A6

A7

A7

A8

A8

A9

A9

A10

A10

B1

B1

B2

B2

B3

B3

B4

B4

B5

B5

B6

B6

B7

B7

B8

B8

B9

B9

B10

B10

C1

C1

C2

C2

C3

C3

C4

C4

C5

C5

C6

C6

C7

C7

C8

C8

C9

C9

C10

C10

D1

D1

D2

D2

D3

D3

D4

D4

D5

D5

D6

D6

D7

D7

D8

D8

D9

D9

D10

D10

E1

E1

E2

E2

E3

E3

E4

E4

E5

E5

E6

E6

E7

E7

E8

E8

E9

E9

E10

E10

F1

F1

F2

F2

F3

F3

F4

F4

F5

F5

F6

F6

F7

F7

F8

F8

F9

F9

F10

F10

GND

_G1

G1

GND

_G2

G2

GND

_G3

G3

GND

_G4

G4

GND

_G5

G5

GND

_G6

G6

GND

_G7

G7

GND

_G8

G8

GND

_G9

G9

GND

_G10

G10

GND

_H

1

H1

GND

_H

2

H2

GND

_H

3

H3

GND

_H

4

H4

GND

_H

5

H5

GND

_H

6

H6

GND

_H

7

H7

GND

_H

8

H8

GND

_H

9

H9

GND

_H

10

H10

GND

_J

1

J1

GND

_J

2

J2

GND

_J

3

J3

GND

_J

4

J4

GND

_J

5

J5

GND

_J

6

J6

GND

_J

7

J7

GND

_J

8

J8

GND

_J

9

J9

GND

_J

10

J10

GND

_K1

K1

GND

_K2

K2

GND

_K3

K3

GND

_K4

K4

GND

_K5

K5

GND

_K6

K6

GND

_K7

K7

GND

_K8

K8

GND

_K9

K9

GND

_K10

K10

GND

_L1

L1

GND

_L2

L2

GND

_L3

L3

GND

_L4

L4

GND

_L5

L5

GND

_L6

L6

GND

_L7

L7

GND

_L8

L8

GND

_L9

L9

GND

_L10

L10

D1

LED

_

Gr

e

e

n

D1

LED

_

Gr

e

e

n

C1

22uF

1206

C1

22uF

1206

J5

HE

A

D

E

R

 3

J5

HE

A

D

E

R

 3

1

2

3

J1

2

HE

A

D

E

R

 2

J1

2

HE

A

D

E

R

 2

1

2

C1

9

0.

01uF

0603

C1

9

0.

01uF

0603

C3

0.

01uF

0603

C3

0.

01uF

0603

C1

8

0.

1uF

0603

C1

8

0.

1uF

0603

J9

HE

A

D

E

R

 3

J9

HE

A

D

E

R

 3

1

2

3

R4

10K

0603

R4

10K

0603

R1

6

0

0603

R1

6

0

0603

R1

0

0

0603

R1

0

0

0603

Q1

BSS138LT

1

Q1

BSS138LT

1

R3

10K

0603

R3

10K

0603

C2

1

22uF

1206

C2

1

22uF

1206

R-even

R-odd

G-even

G-odd

B-even

B-odd

R-in

G-in

B-in

Clk-in

T

F

P401A

U1

R-even

R-odd

G-even

G-odd

B-even

B-odd

R-in

G-in

B-in

Clk-in

T

F

P401A

U1

AGN

D

79

Rx

2

P

80

Rx

2

N

81

AVD

D

82

AGN

D

83

AVD

D

84

Rx

1

P

85

Rx

1

N

86

AGN

D

87

AVD

D

88

AGN

D

89

Rx

0

P

90

Rx

0

N

91

AGN

D

92

Rx

CP

93

Rx

CN

94

AVD

D

95

EXT

_

R

E

S

96

DFO

1

R

S

VD

 (

T

ie

 hi

gh)

99

OC

K_I

N

V

100

PD

N

2

PD

ON

9

PI

XS

4

ST

3

ST

AGN

7

QE4

14

QE5

15

QE6

16

QE7

17

QO8

59

QO9

60

QO10

61

QO11

62

QO12

63

QO13

64

QO14

65

QO15

66

QE8

20

QE9

21

QE10

22

QE11

23

QE12

24

QE13

25

QE14

26

QE15

27

QO16

69

QO17

70

QO18

71

QO19

72

QO20

73

QO21

74

QO22

75

QO23

77

QE16

30

QE17

31

QE18

32

QE19

33

QE20

34

QE21

35

QE22

36

QE23

37

QE2

12

QE3

13

QE0

10

QE1

11

QO6

55

QO1

50

QO0

49

QO3

52

QO7

56

QO4

53

QO2

51

QO5

54

CT

L

3

42

CT

L

2

41

CT

L

1

40

DE

46

HS

Y

N

C

48

OD

C

K

44

VSY

N

C

47

SC

D

T

8

OVD

D

18

OVD

D

29

OVD

D

43

OVD

D

57

OVD

D

78

OGN

D

76

OGN

D

45

OGN

D

58

OGN

D

19

OGN

D

28

DG

ND

5

DG

ND

39

DV

DD

67

DG

ND

68

DV

DD

6

DV

DD

38

PVD

D

97

PGN

D

98

C2

7

0.

001uF

0603

C2

7

0.

001uF

0603

Summary of Contents for 7:1 LVDS

Page 1: ...tion HDL source and bitstream programming files for the LatticeECP2 FPGA a user s guide for the LatticeECP2 Advanced Evaluation Board and other related materials can be downloaded from the Lattice web...

Page 2: ...rialized and transmitted via the LatticeECP2 50 LVDS I Os The remainder of the setup is similar to the video input side but reversed The LVDS signals are fed via a VHDM connector to the Video Demo boa...

Page 3: ...board1 1 2 5V wall mount power adapter1 1 3 Video Demo board 1 1 4 Video Demo board 42 1 5 Video Demo board 2 1 6 Video Demo board 3 1 7 DVI cable 1 8 MDR 26 Channel Link cable 2 9 Black banana plug...

Page 4: ...n pin1 pin2 of J3 J7 J8 J9 J11 J13 and J21 Install jumpers on pin2 pin3 of J10 and J12 Install jumpers on pin1 pin3 of J4 and J6 Install jumper on pin4 pin6 of J5 RS 232 LatticeECP2 50 672 fpBGA LCD 1...

Page 5: ...e set to 3 3V The following table shows the proper jumper settings for the Lattice 7 1 Video Demo Table 2 Jumper Settings for the LatticeECP2 Advanced Board sysIO Bank Jumper Jumper on Pins 0 J14 1 3...

Page 6: ...llator clock output to the LatticeECP2 50 device The locations of these jumpers are shown below Figure 5 Jumper Settings on the LatticeECP2 Advanced Evaluation Board If you are using the optional CP 2...

Page 7: ...Board Figure 6 shows the proper installation of Board 1 Tx side on the left and Board 4 Rx side on the right installed on the LatticeECP2 Advanced Evaluation Board Note in this figure the Board 4 sho...

Page 8: ...m if it is not get ting a proper EDID from the video sink To prevent this from happening you should first set the screen resolution and check if the video stream is transmitting properly to the LCD di...

Page 9: ...lected the push button SW4 needs to be toggled to activate the adjustment Note that once the Auto Demo is enabled the OSD will be moving its position and bounce back when it hits the edge of the displ...

Page 10: ...o Demo Kit at www latticesemi com boards Figure 9 is a representation of the top level VHDL file of this design The gray color blocks shown below are imple mented in other VHDL files The light green c...

Page 11: ...real number 1 0 is represented by the 9 bit binary 100000000 The maximum value of the gains are limited to 1 0 The product of the 9x9 multiplier is an 18 bit value with 10 integer part bits and 8 frac...

Page 12: ...The 4 bit outputs of the serializers are sent to the 2x gearing ODDRX2B modules for pumping out of the LVDS I Os For more information about the transmitter please refer to Lattice reference design RD1...

Page 13: ...d are not compatible Please use a standard DVI source such as a laptop or desktop computer or a Channel Link source to the LVDS No video output when everything is connected There are a number of possi...

Page 14: ...by the Lattice Power Manager II POWR1220AT8 If SW1 Pin 1 is on pushed down the POWR1220AT8 device will be reset and all powers including the 3 3V will be disabled 5 The monitor being used is a VGA mon...

Page 15: ...latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notic...

Page 16: ...input of TFP410 Pin1 and Pin2 high J9 DKEN Data de skew enable control of TFP410 Pin1 and Pin2 high J10 ISEL RSTn This is an active high I2 C select signal of TFP410 used for enabling the TFP410 s I2...

Page 17: ...QO 23 0 and control signals HSYNC VSYNC DE CTL1 3 are latched Pin1 and Pin2 high J6 DFO TFP401A s Output clock data format Controls the output clock ODCK format for either TFT or DSTN panel support P...

Page 18: ...emo Board 1 Figure 14 Video Demo Board 1 Schematic 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Title Size Document Number Rev Date Sheet of A Video Demo Board 1 C 1 2 Title Size Document Number Rev Date Sheet...

Page 19: ...14 TxOut0Gnd 2 TxOut0 15 Sense 3 USB DDC_Gnd 16 TxOut1 4 TxOut1Gnd 17 TxOut1 5 DDC SDA 18 TxOut2 6 TxOut2Gnd 19 TxOut2 7 USB 20 USB_Shield 8 USB 21 DDC SCL 9 TxClkOut 22 TxClkOutGnd 10 TxClkOut 23 USB...

Page 20: ...mo Board 2 Schematic 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Title Size Document Number Rev Date Sheet of A Video Demo Board 2 C 1 2 Title Size Document Number Rev Date Sheet of A Video Demo Board 2 C 1 2...

Page 21: ...PV37W101C01 PV37W 1 3 2 C4 0 001uF 0603 C4 0 001uF 0603 J15 HEADER 10X2 J15 HEADER 10X2 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 C23 0 1uF 0603 C23 0 1uF 0603 C14 0 1uF 0603 C14 0 1uF 0603 C...

Page 22: ...mo Board 3 Schematic 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Title Size Document Number Rev Date Sheet of A Video Demo Board 3 C 1 2 Title Size Document Number Rev Date Sheet of A Video Demo Board 3 C 1 2...

Page 23: ...R11 0 0603 R11 0 0603 C17 22uF 1206 C17 22uF 1206 J15 HEADER 10X2 J15 HEADER 10X2 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 DVI Integrated J1 DVI_I DVI Integrated J1 DVI_I TMDS_Data2 2 TMDS_D...

Page 24: ...o Board 4 Schematic 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Title Size Document Number Rev Date Sheet of A1 Video Demo Board 4 C 1 2 Title Size Document Number Rev Date Sheet of A1 Video Demo Board 4 C 1...

Page 25: ...Shield 19 USB 7 RxIn2 20 RxIn2Gnd 8 RxIn2 21 DDC SDA 9 RxIn1 22 RxIn1Gnd 10 RxIn1 23 USB DDC_Gnd 11 Sense 24 RxIn0 12 RxIn0Gnd 25 RxIn0 13 DDC_Gnd_26 26 Mounting_R 27 Mounting_L 28 J1 MOLEX VHDM 74031...

Page 26: ...Demo Board 1 is not equivalent to Video Demo Board 4 Please modify the lpf preference file of reference design RD1030 LatticeECP2 M 7 1 LVDS Video Interface to match the board that you are using on th...

Page 27: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Lattice LFE2 50E VID EV...

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