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MachXO Standard Evaluation Board

Lattice Semiconductor

Revisions 001 & 002 User’s Guide 

 

Figure 1. MachXO Standard Evaluation Board

 

Power Supply

 

The MachXO Standard Evaluation Board includes two locations to apply power. On the east side of the board are a
pair of banana jacks (JP28 and JP29) and a coaxial DC connector (JP30), which receive power from either a bench
power supply or a brick style power supply. A DC source between 5.0V and 28.0V must be applied in order to
power the board. The coaxial DC connector uses a 2.5mm central pin, with a 6.3mm outer diameter barrel.

The output from the DC system is controlled by switch S5. Switch S5 is in the southeast corner of the board. This is
a small surface mount switch that enables and disables the LTC1775 DC-DC conversion chip. The output voltages
from the power supply are enabled when the switch is in the “on” position.

The 5.0V to 28.0V DC input voltage is converted by DC-DC converters and switching power supplies to provide
3.3V, 1.2V, and an adjustable DC source on the board. The output from these supplies travels through surface
mounted fuse holders. Fuses are supplied and prevent over-current conditions from damaging the components on
the board (Vendor: Littlefuse, Make: Nano SMF Very Fast Acting, 1.5A or 3A).

Due west of the fuse blocks are more banana plug connectors. These connectors provide an alternate means for
applying DC voltage levels to the board. To apply voltages not supplied by the on-board power section, 

 

first

remove the appropriate fuse from the fuse holder

 

. Then connect an alternate DC supply to the banana plug

connector associated with that fuse.

 

Table 1. Power Supply Fuses

 

Fuse Number

Supply Rail 

Enabled/Disabled

Banana Connector 

Input

 

F1

V

 

ADJ

 

JP25

F2

1.2V

JP26

F3

3.3V

JP27

RJ-45
Connector
Area

SMA
Connector
Area

ispClock5610

DIP Oscillator

8-Bit Input 

Switch

Push-Button 

Switches

Prototype

Areas

LCD Display

Area

DC Power

Input Jack

Power
Inputs

North

South

East

West

Prototype

Area

JTAG Pro

g

rammin

g

Interface

Summary of Contents for MachXO

Page 1: ...March 2008 Revision EB21_01 6 MachXO Standard Evaluation Board Revisions 001 002 User s Guide...

Page 2: ...lock input general purpose I O pins RJ 45 connector not populated LCD GPIO footprint 100mil center center test point grid Impedance controlled Mictor not populated General Description The heart of the...

Page 3: ...ches are not all ON or all OFF the LEDs for the switches that are ON will light up Additionally other I Os on the MachXO device are also toggled using the internal counter outputs See the source code...

Page 4: ...t voltage is converted by DC DC converters and switching power supplies to provide 3 3V 1 2V and an adjustable DC source on the board The output from these supplies travels through surface mounted fus...

Page 5: ...e 2 MachXO Standard Evaluation Board Programmability The programming interface for the MachXO and ispClock5610 is located in the northwest corner of the board The 1x10 header JP7 is the connection poi...

Page 6: ...ate it is necessary to instantiate the GSR macro in the VHDL Verilog HDL source Immediately adjacent to the MachXO reset switch is the ispClock reset switch S3 Pressing this button asserts RESET to th...

Page 7: ...rids The board includes five 100 mil center center prototype grid areas consisting of plated through holes with various connections It is important to note the board conventions used to identify the t...

Page 8: ...points The MachXO I O pin connec tions are indicated in the silkscreen marking For example the top left location connects to MachXO pin F5 etc These test points are directly connected to the MachXO w...

Page 9: ...ve element seven segement LCD display When this display is populated it is mounted on the rows between U3 and JP23 JP24 JP23 and JP24 can then be populated with general purpose headers Jumpers can the...

Page 10: ...osition the switch is tied to ground Table 8 Switch Assignments Oscillator and Clock Inputs The MachXO Standard Evaluation Board provides the ability to supply selectable reference frequencies to the...

Page 11: ...e of the board are two resistor sites R158 and R159 R158 connects XU2 pin 10 to the ispClock5610 positive clock input R159 connects JP4 to the ispClock positive clock input By default R158 has a zero...

Page 12: ...s The profiles are selected using the PS1 0 input pins The ispClock is programmed with a unique personality in profile 0 None of the remaining profiles provide additional frequencies Profile 0 is conf...

Page 13: ...l Lattice trademarks registered trademarks patents and disclaimers are as listed at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respecti...

Page 14: ...C 1 12 Title Size Document Number Rev Date Sheet of Doc 0 MachXO Evaluation Board C 1 12 Title Size Document Number Rev Date Sheet of Doc 0 MachXO Evaluation Board C 1 12 Page 2 Page 3 Page 4 Page 5...

Page 15: ...F CC0402 Populate C16 0 1uF CC0402 Populate R61 100 CR0603 NoPopulate R61 100 CR0603 NoPopulate C17 10uF CC0805 Populate C17 10uF CC0805 Populate R45 100 CR0603 NoPopulate R45 100 CR0603 NoPopulate C1...

Page 16: ...pF CC0603 Populate C31 2200pF CC0603 Populate J56 JBLOCK Populate J56 JBLOCK Populate R153 10 CR0603 Populate R153 10 CR0603 Populate R145 0 005 602SJ Populate R145 0 005 602SJ Populate F1 3A 383milX1...

Page 17: ...EVEN D12 14 EVEN D11 16 EVEN D10 18 EVEN D9 20 EVEN D8 22 EVEN D7 24 EVEN D6 26 EVEN D5 28 EVEN D4 30 EVEN D3 32 EVEN D2 34 EVEN D1 36 EVEN D0 38 GND_0 39 GND_1 40 GND_2 41 GND_3 42 GND_4 43 M1 MOUNT...

Page 18: ...25 BANK_3B 26 BANK_3A 27 GNDO_3 28 VCCO_4 29 BANK_4B 30 BANK_4A 31 GNDO_4 32 VCCA 13 GNDA 14 SGATE 40 GOE 42 OEX 21 OEY 22 LOCK 34 TDI 39 TDO 35 TMS 37 TCK 38 TEST1 46 TEST2 45 GNDD_0 23 GNDD_1 48 VCC...

Page 19: ...te COM 1 1G 2 QE 3 1D 4 1C 5 2E 6 2D 7 2C 8 3E 9 3D 10 3C 11 DP3 12 4E 13 4D 14 4C 15 DP4 16 5E 17 5D 18 5C 19 5B 20 5A 21 5F 22 5G 23 4B 24 4A 25 F4 26 4G 27 3B 28 3A 29 3F 30 3G 31 DP2 32 2B 33 2A 3...

Page 20: ...ard C 7 12 Title Size Document Number Rev Date Sheet of Doc 0 MachXO Evaluation Board C 7 12 73 59 45 0 58 46 95 74 Page 8 Page 9 Page 10 Page 11 The series resistors with a short circuit should be pl...

Page 21: ...K CR0603 NoPopulate TP165 TEST POINT TP165 TEST POINT 1 TP137 TEST POINT TP137 TEST POINT 1 TP104 TEST POINT TP104 TEST POINT 1 R170 1K CR0603 NoPopulate R170 1K CR0603 NoPopulate TP78 TEST POINT TP78...

Page 22: ...OINT 1 TP400 TEST POINT TP400 TEST POINT 1 TP392 TEST POINT TP392 TEST POINT 1 TP300 TEST POINT TP300 TEST POINT 1 TP316 TEST POINT TP316 TEST POINT 1 TP375 TEST POINT TP375 TEST POINT 1 TP377 TEST PO...

Page 23: ...opulate TP197 TEST POINT TP197 TEST POINT 1 R202 1K CR0603 NoPopulate R202 1K CR0603 NoPopulate R235 1K CR0603 NoPopulate R235 1K CR0603 NoPopulate TP235 TEST POINT TP235 TEST POINT 1 TP268 TEST POINT...

Page 24: ...n Board C 11 12 Title Size Document Number Rev Date Sheet of Doc 0 MachXO Evaluation Board C 11 12 TP44 TEST POINT TP44 TEST POINT 1 TP21 TEST POINT TP21 TEST POINT 1 TP56 TEST POINT TP56 TEST POINT 1...

Page 25: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Lattice LCMXO640C L EV LS X2280 BASE PC N...

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