9
ispClock5400D Evaluation Board
Lattice Semiconductor
User’s Guide
4.
Position the mouse over the rising edge of the
Bank2 Time waveform
.
The cursor will changes to a double-arrow icon to indicate a waveform edit.
5.
Click and hold the
Bank 2 Time waveform
, then drag it three units to the right.
The Setting field displays 3 and Time Skew (ps) displays 54.00.
6.
Click the
Write to Schematic
button.
PAC-Designer updates the time skew setting of the project.
7.
Click the
Download
icon on the top toolbar.
The Frequency Summary dialog appears and reports the Reference and VCO frequency settings.
8.
Click
OK
.
PAC-Designer reprograms the evaluation board with the updated JEDEC programming file.
9.
Note the updated scope display.
This waveform shows the de-skewed outputs.
Figure 9. Scope Plot - De-skewed Outputs
The programmable ispClock5406D Time Skew feature allows the device to account for very small incremental
delays and correct for system/board trace-level effects. The function is used to correct timing delays and line up
edges to either account for PCB layout or to help with clock system timing such as the set-up and hold times of
the circuit being driven.
Experiment with the Time Skew and visualize the results on the scope. The demo design time skew range
allows you to move clock edges from 18 ps to 270 ps. When finished, set back to the Time-Skew that yields the
best results for your set-up.
