18
ispClock5400D Evaluation Board
Lattice Semiconductor
User’s Guide
Figure 20. ispClock5406D Soft Reset Dialog - Soft Reset Released State
4.
Click
OK
.
Note the scope display changes to reflect the time-skewed waveform pattern produced earlier. I
2
C commands
will be retained and reapplied after soft reset has been released.
5.
Click the
Full Reset
button.
The ispClock5406D Full Reset dialog prompt appears and the I
2
C utility issues the I
2
C command to assert full
reset. During this state, all configuration registers are updated from the E
2
CMOS configuration. All the values
loaded by I
2
C are overwritten. This command is equivalent to toggling the RESETb pin of the ispClock5406D
device. The differential outputs of the ispClock5406D banks are disabled during the full reset state.
6.
Click
OK
.
7.
Click the
Full Reset
button.
The ispClock5406D Full Reset dialog prompt appears and the I
2
C utility issues the I
2
C command to release full
reset. When released from a full reset the device reverts back to the configuration state that is defined and
stored in E
2
CMOS.
8.
Click
OK
.
Note the scope display changes to reflect the original waveform pattern produced by the initial ispClock5406D
device programming.
You have completed the ispClock5406D Base Demo. You can try other in-system device configurations using the
I
2
C utility or modify the PAC-Designer project then reprogram the device.
Period Jitter Measurement
The demo consists of setting up the ispClock5400D Evaluation Board hardware and a Wavecrest (Gigamax) SIA-
3000D analyzer to demonstrate the ultra-low phase jitter of the ispClock5406D device.
How to set up the SIA-3000D:
1.
From the SIA-3000D, GigaView software, perform Extended Timer Calibration (>=11min calibration).
2.
Open the Clock Analysis Tool and set up for a Period Jitter measurement.
Set up the base demo project for a phase jitter measurement:
1.
Use PAC-Designer to open the
Base_Demo_CLK5406D.PAC
project.
2.
Save the Base_Demo_CLK5406D.PAC as
Base_Demo_CLK5406D_jitter.pac
.
3.
Choose
Edit > Symbol...
The Edit Symbol dialog appears.
4.
Choose
REF Frequency
and click
Edit...
The PLL Core Settings dialog appears.
