Himax HM01B0 UPduino Shield
User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at
www.latticesemi.com/legal
.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02081-1.0
17
Figure A.3. UPduino 2.0 FTDI Chip Connection
FT232HQ
+5V
GND
GND
C
S
T
C
R
12M
H
z
GND
1.8V
+
3V
3
GND
+
3V
3
+
3V
3
GND
+
3V
3
GND
G
N
D
93LC56B
gre
e
n
re
d
+
3V
3
+
3V
3
+
3V
3
GND
+5V
GND
+5V
G
N
D
GND
IC2
ADBUS0/TXD
13
ADBUS1/RXD
14
ADBUS2/RTS#
15
ADBUS3/CTS#
16
ADBUS4/DTR#
17
ADBUS5/DSR#
18
ADBUS6/DCD#
19
ADBUS7/RI#
20
ACBUS0/TXDEN
21
ACBUS1
25
ACBUS2
26
ACBUS3/RXLED#
27
ACBUS4/TXLED#
28
ACBUS5
29
ACBUS6
30
ACBUS7
31
VREGIN
40
VCCCORE
38
USBD-
6
USBD+
7
REF
5
RESET
34
G
N
D
4
8
G
N
D
4
7
G
N
D
3
6
G
N
D
3
5
G
N
D
2
3
G
N
D
2
2
G
N
D
1
1
G
N
D
1
0
A
G
N
D
4
EECS
45
EECLK
44
EEDATA
43
OSCIN
1
OSCOUT
2
TEST
42
VCCD
39
V
C
C
IO
4
6
V
C
C
IO
2
4
V
C
C
IO
1
2
V
P
L
L
8
V
P
H
Y
3
VCCA
37
A
G
N
D
9
A
G
N
D
4
1
ACBUS8
32
ACBUS9
33
PAD
THERMAL
Q
1
VCC
GND
IC1
6
2
CLK
4
DO
1
DI
3
CS
5
L
E
D
1
L
E
D
2
D+
D-
VBUS
GND
ID
MT1*4
+5V
D+
D+
D-
D-
GND
OSC_OUT
C8
C9
C7
ICE_SCK
D3
ICE_SS
D5
D6
CRESET_B
C0
C1
C2
C3
C4
C5
C6
FLASH_MOSI
FLASH_MISO
A
rr
a
y
E
E
P
R
O
M
A
B
C
D
1
2
3
4
5
6
A
B
C
D
1
2
3
4
5
6
o
gtjennings_pcb_121217_1200_release
12/12/2017 8:04 AM
2014
C
ISSUE
DRAWN
CHECKED
DATE
>COMPANY
>DRAWN
>CHECKED
>DATE
>DRGNO
>REV
U
S
B
