Lattice Semiconductor EVDK User Manual Download Page 9

 

EVDK GigE Vision Demo 

 

User Guide 

 

© 2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at 

www.latticesemi.com/legal

 

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-UG-02100-1.0 

 

3.

 

Configuring and Running the GigE Video Streaming Demo 

The GigE video streaming demo consists bit-streams for the ECP5 FPGA. This demo has its own bit-stream file for 
Ethernet. It is assumed that the board setup is configured with bitstream for CrossLink and ECP5 as illustrated in the 

Demo Board Setup

 section. 

The following sections describe the demo. 

3.1.

 

Configuring the GigE Demo 

To configure the GigE demo:  

1.

 

Ensure that you have a video viewer installed on your PC which supports GigE video streaming. This demo uses 
eBUS Player by Pleora Technologies, which is a Windows based video capture software. Any other software 
supporting GigE video streaming can be used. 

2.

 

Ensure that power is connected to the board. 

3.

 

Configure the network parameters of the destination PC with static IP address of 169.254.18.198 and subnet mask 
255.255.0.0, as described in Appendix A. The default source IP address of the USB3-GigE VIP IO Board is hard coded 
in the RTL code to 169.254.0.2.  

Note: It is recommended to write down your original settings so you can restore your PC to its normal settings 
afterward. 

4.

 

Connect the Ethernet cable between the USB3-GigE VIP IO Board and the PC. 

3.2.

 

Running the GigE Demo 

To set up the board for camera streaming: 

1.

 

Power cycle the EVDK 

2.

 

Press the reset button on the Crosslink board (SW3). 

 

To set up the eBUS Player for camera streaming: 

1.

 

Turn off firewall of the computer. 

2.

 

Open the eBUS Player software. 

 

Figure 3.1. eBUS Player GUI 

Summary of Contents for EVDK

Page 1: ...EVDK GigE Vision Demo User Guide FPGA UG 02100 1 0 February 2020...

Page 2: ...aults and all risk associated with such information is entirely with Buyer Buyer shall not rely on any data and performance specifications or parameters provided herein Products sold by Lattice have b...

Page 3: ...E Demo 9 3 2 Running the GigE Demo 9 Appendix A Changing Network Connection to Static IP Address 13 References 15 Technical Support Assistance 16 Revision History 17 Figures Figure 1 1 2 1 MIPI CSI 2...

Page 4: ...rademarks of their respective holders The specifications and information herein are subject to change without notice 4 FPGA UG 02100 1 0 Acronyms in This Document A list of acronyms used in this docum...

Page 5: ...s a Sony IMX214 camera to output 1080p video over four MIPI data lanes each running at 371 25 Mb s The CrossLink Video Interface Platform VIP Input Bridge Board receives the MIPI video stream from the...

Page 6: ...configuration which is designed as a stackable modular architecture with 80 mm 80 mm form factor The Embedded Vision Development Kit consists of three boards CrossLink VIP Input Bridge Board ECP5 VIP...

Page 7: ...Vision Development Kit the following items are required to demonstrate GigE video streaming USB3 GbE VIP IO Board Ethernet cable Figure 1 5 USB3 Gbe VIP IO Board Rev B 1 3 Software Requirements Before...

Page 8: ...ve the HDMI VIP Output Bridge Board 3 Install the USB3 GbE VIP IO Board a Connect J1 60 pin connector to J12 of the ECP5 VIP Processor Board b Connect J2 60 pin connector to J13 of the ECP5 VIP Proces...

Page 9: ...deo viewer installed on your PC which supports GigE video streaming This demo uses eBUS Player by Pleora Technologies which is a Windows based video capture software Any other software supporting GigE...

Page 10: ...ered trademarks of their respective holders The specifications and information herein are subject to change without notice 10 FPGA UG 02100 1 0 3 Click Tools Setup 4 Set the parameters as shown in Fig...

Page 11: ...names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice FPGA UG 02100 1 0 11 Figure 3 4 eBUS Player Bu...

Page 12: ...arks patents and disclaimers are as listed at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and info...

Page 13: ...hange without notice FPGA UG 02100 1 0 13 Appendix A Changing Network Connection to Static IP Address To change network connection to static IP address 1 Select Control Panel Network and Sharing Cente...

Page 14: ...ticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice 1...

Page 15: ...e following documents For more information on boards and kits available for the VIP Video Interface Platform system visit www latticesemi com vip For more information on the Embedded Vision Developmen...

Page 16: ...s listed at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to chan...

Page 17: ...s are as listed at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject...

Page 18: ...www latticesemi com...

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