CrossLink-NX Evaluation Board
User Guide
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.
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54
FPGA-EB-02028-1.3
Appendix D. Schematics Updates for ADC Test
Early versions of the schematic (
Appendix A
) contained errors, with pin swaps in Bank 0 and ADC symbol parts
(reference designators U3A and U3K, respectively). These symbol errors have been corrected in the current schematic
(Revision B-1 and later).
As a result of the original error, the ADC channel 0 test access circuit is connected incorrectly: J24 is connected to the
negative input and J25 is connected to the positive input (see
Figure A.9
).
To effectively utilize the ADC test access circuit on the Crosslink-NX Evaluation Board Revision B, follow these
guidelines:
For single-ended use, voltages applied to J25-2 should be positive relative to voltages applied to J24-2. Do not use
shunt position 1-2 for either J24 and J25.
For single-ended testing utilizing the voltage generated by the 10 KΩ potentiometer U8:
Use a jumper wire to connect J24-1 and J25-2, connecting the POT to channel 0 POS input (ADC_DP0).
Use a jumper wire to connect J24-2 and J25-1, connecting channel 0 NEG input (ADC_DN0) to ground.
For differential testing, connect the signals directly to Pin 2 of J24 and J25, or use header J26.
To route the ADC signals to header J26, use shunt positions 2-3 of both J24 and J25 to connect ADC_DN0 to
connector J26-3 and ADC_DP0 to connector J26-5.
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