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CrossLink-NX Evaluation Board
User Guide
© 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at
www.latticesemi.com/legal
.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-EB-02028-1.3
8.6.
PMOD Header
The J17, J18 and J19 header can be used as GPIO or as a connector to a PMOD interface.
Table 8.6. J17, J18 and J19 Header Pin Connections
Pin Name
Signal Name
LIFCL-40 Ball
J17 Pin Name
1
PMOD0_1
D10
2
PMOD0_2
D9
3
PMOD0_3
D7
4
PMOD0_4
D8
5
PMOD0_7
D6
6
PMOD0_8
D5
7
PMOD0_9
D4
8
PMOD0_10
D3
J18 Pin Name
1
PMOD1_1
E10
2
PMOD1_2
E9
3
PMOD1_3
E7
4
PMOD1_4
E8
5
PMOD1_7
E4
6
PMOD1_8
E3
7
PMOD1_9
E2
8
PMOD1_10
F1
J19 Pin Name
1
PMOD2_1
J2
2
PMOD2_2
J1
3
PMOD2_3
K2
4
PMOD2_4
K1
5
PMOD2_7
K3
6
PMOD2_8
K4
7
PMOD2_9
D17
8
PMOD2_10
E18
8.7.
JTAG Header
The J1 header is used to access the JTAG port of the CrossLink-NX or the Raspberry Pi interface.
Table 8.7. J1 Header Pin Connections
J1 Pin Name
Signal Name
LIFCL-40 Ball
1
VCCIO1
—
2
TDO
F19
3
TDI
F17
4
No Connect
—
5
No Connect
—
6
TMS
F15
7
GND
—
8
TCK
E19
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