Lattice Semiconductor CrossLink-NX ISP Demo, Quick Start Manual

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Lattice CrossLink-NX ISP Demo Quick Start Guide
Application Note
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal .
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
6 FPGA-AN-02040-1.0
2. ISP Reference Design Block Diagram
The ISP reference design captures sensor data, converts its interfaces, implements ISP pipelines, and finally displays the
video on the HDMI monitor.
Figure 2.1 shows the whole ISP reference design architecture and data flow.
HDMI
Transmitter
Monitor
IMX258
CrossLink-
NX
ECP5
MIPI 4 Lane
Parallel Parallel
I
2
C
Figure 2.1. ISP Reference Design Architecture and Data Flow
The ISP core is implemented in the CrossLink-NX device. The CrossLink-NX device receives the MIPI sensor data,
converts it to the parallel interface, implements ISP processing, and transmits the video to the HDMI transmitter.
Figure 2.2 shows the Crosslink-NX ISP block diagram.
BLC
ISP Core
DPC CFI AWB AE CCM TMAP GAMMA HDMI
Figure 2.2. CrossLink-NX ISP Block Diagram