POWER
AMPLIFIER
1.5KW
HIGH
BAND
40D1493G3
PUB96
‐
29
Rev
2
August
2007
29-3
PA
Module
operating
transmitter,
it
provides
protection
to
the
FETs
against
over
‐
dissipation
due
to
high
VSWR,
and
it
monitors
the
module
RF
power
gain.
If
the
module
is
plugged
into
a
powered
transmitter
using
several
modules
running
in
parallel,
the
power
supply
connections
are
first
made
through
the
longer
contacts
of
the
module’s
DC
power
connector
and
into
VSWR
board
J1
pin
8.
This
allows
the
electrolytic
bypass
capacitors
of
all
amplifiers
to
charge
through
current
limiting
resistor
R5,
preventing
overstress
of
all
amplifier
fuses
due
to
charge
current
of
the
bypass
capacitors.
When
the
module
is
fully
seated,
the
high
current
contacts
are
connected
and
the
module
can
operate
normally.
In
normal
operation
the
power
supply
enters
J1
via
pin
2,
and
is
regulated
to
+39
VDC
by
series
resistor
R10
and
zener
diode
VR1.
Regulator
U1
provides
constant
B+
voltage
for
op
‐
amps
U2,
U3,
U4,
and
the
comparator
reference
voltages.
When
the
module
is
first
turned
on
(or
plugged
in)
and
U1
begins
regulating,
the
charging
current
of
C7
turns
on
Q1
which
pulls
the
bias
line
low
for
a
brief
period
of
time.
This
provides
a
slow
start
for
the
module
after
DC
power
is
applied.
The
overall
RF
system
of
the
transmitter
provides
overall
VSWR
protection
via
the
external
RF
detector
boards
discussed
in
other
sections
of
this
manual,
but
VSWR
sensing
is
also
provided
in
the
module
for
its
own
safety.
In
the
transmitters
utilising
modules
in
parallel,
one
or
more
failed
or
disconnected
modules
or
a
fault
in
the
six
‐
way
combiner
or
subsequent
3
dB
coupler,
may
cause
a
module
output
mismatch.
To
the
module,
any
mismatch
which
appears
as
reflected
power
is
detected
and
sensed
at
pin
11
of
J1
to
comparator
circuit
U2B.
R21
sets
the
level
at
which
VSWR
protection
begins.
If
the
level
of
detected
reflected
power
on
pin
5
of
U2B
exceeds
the
control
voltage
set
on
pin
6,
the
output
on
pin
7
will
go
high.
R22,
C10,
and
CR1
provide
a
fast
attack,
slow
release
control
voltage
to
Q2
when
a
high
VSWR
condition
suddenly
occurs.
This
will
turn
on
Q2
which
turns
on
Q4
which
quickly
reduces
the
bias
applied
to
the
power
amplifier
FETs;
this
reduced
bias
also
reduces
their
gain
and
therefore
their
RF
output
and
keeps
the
amplifier
at
safe
levels.
When
a
module
is
plugged
into
an
operating
transmitter,
the
slow
start
circuitry
consisting
of
C7
and
Q1
will
initially
keep
the
module
turned
off.
Power
from
the
other
modules
working
into
the
combiner
will
enter
the
module
and
be
detected
by
the
reflected
power
detector.
This
would
prevent
the
module
from
ever
operating
properly,
unless
the
VSWR
circuit
is
momentarily
over
‐
ridden.
The
circuit
of
U4
produces
a
pulse
approximately
2
seconds
after
power
is
applied
to
the
module.
At
power
‐
up,
pin
2
of
U4
will
be
pulled
high
by
C11.
R26
charges
this
capacitor,
and
when
the
pin
2
voltage
goes
below
the
voltage
on
pin
3,
the
output
of
U4
will
go
high.
A
pulse
whose
duration
is
controlled
by
C9
and
R18
will
then
be
applied
to
pin
3
of
U2A.
U3B
detects
that
the
module
is
not
producing
forward
power
and
that
the
reverse
power
is
high.
Under
these
conditions
the
output
of
U2A
goes
high,
turning
on
Q3,
momentarily
disabling
VSWR
protection,
and
allowing
the
module
to
come
on.
DC
samples
corresponding
to
forward
power
into
and
out
of
the
module
are
applied
to
U3A
pins
2
and
3
respectively.
When
pin
3
voltage
is
higher
than
that
of
pin
2,
corresponding
to
"RF
gain
is
okay"
the
comparator
output
U3A
pin
1
is
high,
causing
the
green
LED
on
the
front
panel
of
the
module
to
light.
The
comparison
threshold
(ie.
module
gain
is
ok)
is
set
by
adjustment
of
R4.
