3: Open-Q 660 µSOM Development Kit
Open-Q™ 660 µSOM Dev Kit User Guide
33
Table 10. Digital IO Expansion Header J2200 Pinout
Pin
No
Signal
Description
Pin
No
Signal
Description
1
VREG_L13A_1P8
PMIC LDO Regulator L13A.
1.8V
2
VREG_L13A_1P8
PMIC LDO Regulator
L13A. 1.8V
3
GPIO_0_BLSP1_S
PI_MOSI
APQ BLSP1 SPI, GPIO_0.
Master output
4
MB_VREG_3P3
Carrier board switching
regulator. 3.3V
5
GPIO_1_BLSP1_S
PI_MISO
APQ BLSP1 SPI, GPIO_1.
Master input
6
No Net
7
GPIO_2_BLSP1_S
PI_CS_N
APQ BLSP1 SPI, GPIO_2.
Chip Select
8
No Net
9
GPIO_3_BLSP1_S
PI_CLK
APQ BLSP1 SPI, GPIO_3.
Clock
10
No Net
11
GND
Ground
12
LPI_GPIO_14_UA
RT_2_TX
Low Power APQ
GPIO_14, UART TX
13
No Net
14
LPI_GPIO_15_UA
RT_2_RX
Low Power APQ
GPIO_15, UART RX
15
No Net
16
No Net
17
GND
Ground
18
GND
Ground
19
MB_VREG_5P0
Carrier board switching
regulator. 5.0V
20
MB_VREG_5P0
Carrier board switching
regulator. 5.0V
For more details regarding configuring the GPIOs on this header, refer to the Open-Q 660 Software Release
Notes to determine feature support in the latest software release.
