Chapter 3 BIOS Setup
42
User’s Manual
PCI Master 0 WS Write: When enabled, writes to the PCI bus and are executed with zero wait states.
The settings are “Enabled” or Disabled”.
PCI Delay Transaction: The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select “Enabled” to support compliance with PCI specification version 2.1. The
settings are “Enabled” or “Disabled”.
PCI#2 Access #1 Retry: When disabled, PCI#2 will not be disconnected until access finishes. When
enabled, PCI#2 will be disconnected if max retries are attempted without success. The default setting is
“Enabled”.
AGP Master 1 WS Write: Implements a single delay when writing from the AGP Bus. Normally, two wait
states are used, allowing for greater stability, but check with your motherboard manufacturer to see if they
have already implemented a Master latency of zero, in which case the lowest writing here of 1 will reduce
performance.
AGP Master 1 WS Read: Implements a single delay when reading from the AGP Bus. Normally, two wait
states are used, allowing for greater stability, but check with your motherboard manufacturer to see if they
have already implemented a Master latency of zero, in which case the lowest reading here of 1 will reduce
performance.
Summary of Contents for EM-660 Series
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