Laird BL654PA, User Manual

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The coin cell operation of BL654PA module on the DVK-BL654PA devboard is NOT possible . A J34 coin cell holder cannot
be used on the DVK-BL654PA SW6 default and only valid position is 3V3/1V8 . SW6 position coin cell is not valid for the
BL654PA.
The development board has a reset button (SW3) with the net name BOOT_RESET_BLE. The BOOT_RESET_BLE (active
low when SW3 pushed down) is routed to the BL654PA module nRESET_BLE pin via an analog switch U25. The placement
of the Reset button is shown in
Figure 6 .
Figure 6: Reset button placement
Figure 7: Reset button schematic and routing through analog switch and location diagram
By default, whether the analog switch (U25) control line (USB_DETECT) is low (USB2 cable not plugged in) or high (USB2
cable plugged in), the nReset button (SW3) is routed via the analog switch (U25) to BL654PA nReset pin (nRESET_BLE).
The development board has USB2 cable detection circuit that generates the USB_DETECT signal on its output, so if a USB
cable is plugged into connector USB2, then USB2 cable detection circuit generates a HIGH on USB_DETECT or LOW if USB2
cable is not plugged in.
Table 2 displays the routing of SW3 reset button via analog switch U25 to the BL654PA reset pin (regardless of whether the
USB cable is plugged into USB2 or not).
C63
NOPOP (0.01uF,16V)
GND
NOPOP (PIN HEADER,2.54mm 1X2P)
J42
1
1
2
2
GND
R34
150R
Reset
SW3
TACT SW,SMD/180d
1
1
2
2
3
3
4
4
BOOT_RESET_BLE
GND
SB22
NOPOP (Solderbridge)
1
1
2
2
BOOT_RESET_BLE
IMCU_BOOT
R114 0R
VDD_VSRC_nRF
U25
Dual DPDT,1.65V~4.45V
1B0
1
1B1
15
2B0
5
2B1
3
1A
16
2A
4
1S
2
3B0
9
3B1
7
4B0
13
4B1
11
3A
8
4A
12
2S
10
GND
6
VCC
14
nRESET_BLE
GND
USB_DETECT
GND
C79
0.1uF,16V