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MITX-CFL0 Series - User Guide, Rev. 1.1
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Table 38: Pin Assignment PCIEX16
Pin
Side B
Side A
Signal
Description
Signal
Description
1
+12V
+12 V power
PRSNT1#
Hot plug presence detect
2
+12V
+12 V power
+12V
+12 V power
3
Reserved
+12V
+12 V power
4
Ground
Ground
5
SMCLK
SMBus clock
Reserved
6
SMDAT
SMBus data
Reserved
7
Ground
Reserved
8
+3.3V
+3.3 V power
Reserved
9
Reserved
+3.3V
+3.3 V power
10
+3.3VSB
+3.3 V standby power
+3.3V
+3.3 V power
11
WAKE#
Link reactivation
PERST#
PCI Express reser
Mechanical Key
12
Reserved
Ground
13
Ground
Reference clock differential pair (+)
14
HSOP0
Lane 0 transmitter differential pair (+) REFCLK-
Reference clock differential pair (-)
15
HSON0
Lane 0 transmitter differential pair (-) Ground
16
Ground
HSIP0
Lane 0 receiver differential pair (+)
17
PRSNT2#
Hot plug presence detect
HSIN0
Lane 0 receiver differential pair (-)
18
Ground
Ground
19
HSOP1
Lane 1 transmitter differential pair (+) Reserved
20
HSON1
Lane 1 transmitter differential pair (-) Ground
21
Ground
HSIP1
Lane 1 receiver differential pair (+)
22
Ground
HSIN1
Lane 1 receiver differential pair (-)
23
HSOP2
Lane 2 transmitter differential pair (+) Ground
24
HSON2
Lane 2 transmitter differential pair (-) Ground
25
Ground
HSIP2
Lane 2 receiver differential pair (+)
26
Ground
HSIN2
Lane 2 receiver differential pair (-)
27
HSOP3
Lane 3 transmitter differential pair (+) Ground
28
HSON3
Lane 3 transmitter differential pair (-) Ground
29
Ground
HSIP3
Lane 3 receiver differential pair (+)
30
Reserved
HSIN3
Lane 3 receiver differential pair (-)
31
PRSNT2#
Hot plug presence detect
Ground
32
Ground
Reserved
33
HSOP4
Lane 4 transmitter differential pair (+) Reserved
34
HSON4
Lane 4 transmitter differential pair (-) Ground
35
Ground
HSIP4
Lane 4 receiver differential pair (+)
36
Ground
HSIN4
Lane 4 receiver differential pair (-)
37
HSOP5
Lane 5 transmitter differential pair (+) Ground
38
HSON5
Lane 5 transmitter differential pair (-) Ground