Kontron MITX-CFL0 Series, User Manual

Page: 57 / 104

MITX-CFL0 Series - User Guide, Rev. 1.1
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Pin Signal Description
27 GND Ground
28 NC
29 PETn1 PCIe Lane 1 transmitter pair (-)
30 NC
31 PETp1 PCIe Lane 1 transmitter pair (+)
32 NC
33 GND Ground
34 NC
35 PERn1 PCIe Lane 1 receiver pair (-)
36 NC
37 PERp1 PCIe Lane 1 receiver pair (+)
38 DEVSLP Device sleep
39 GND Ground
40 NC
41 PETn0/SATAB+ PCIe Lane 0 transmitter pair (-) / SATA transmitter differential pair (+)
42 NC
43 PETp0/SATAB- PCIe Lane 0 transmitter pair (+) / SATA transmitter differential pair (-)
44 NC
45 GND Ground
46 NC
47 PERn0/SATAA- PCIe Lane 0 receiver pair (-) / SATA receiver differential pair (-)
48 NC
49 PERp0/SATAA+ PCIe Lane 0 receiver pair (+) / SATA receiver differential pair (+)
50 PERST PCIe reset
51 GND Ground
52 CLKREQ Reference clock request signal
53 REFCLKN PCIe reference clock pair (-)
54 PEWAKE PCIe wake
55 REFCLKP PCIe reference clock pair (+)
56 NC
57 GND Ground
58 NC
59 KEY M
60 KEY M
61 KEY M
62 KEY M
63 KEY M
64 KEY M
65 KEY M
66
KEY M
67 NC
68 SUSCLK 32.768 kHz clock supply input